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Infineon Technologies CYT2B94BACQ0AZSGST
- Part No.:
- CYT2B94BACQ0AZSGST
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 80-LQFP
- Datasheet:
-
CYT2B94BACQ0AZSGST.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 80LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,751
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Product details
Overview
CYT2B94BACQ0AZSGST from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112-KB code-flash with RWW support, 256-KB SRAM, and integrated CAN FD (up to 8 channels), LIN (up to 12 channels), and CXPI (up to 4 channels). It targets body control modules requiring ASIL-B functional safety, secure boot, and hardware crypto acceleration including AES-128/192/256, SHA-256/512, and ECC.
For engineers reviewing the CYT2B94BACQ0AZSGST datasheet, CYT2B94BACQ0AZSGST pinout, CYT2B94BACQ0AZSGST application, or CYT2B94BACQ0AZSGST equivalent, this part delivers verified dual-CPU partitioning for real-time control + security offload, hardware-enforced memory protection (MPU/SMPU), SECDED ECC on flash/SRAM, and production-ready automotive qualification per AEC-Q100 Grade 2 (–40°C to +105°C).
Technical Context
The device implements strict hardware isolation between M4F (application processing) and M0+ (peripheral/security management) via dedicated inter-processor communication (IPC) registers and PPU-enforced peripheral access control. Its clock architecture integrates IMO, ILO, ECO, WCO, PLL, and FLL with CSV supervision and BOD thresholds at 2.7 V/3.0 V (VDDD/VDDA) and 1.1 V (VCCD).
All safety-critical memories employ SECDED ECC; crypto engine supports eSHE-compliant secure boot with digital signature verification and HSM-level key management. TCPWM blocks (75×16-bit, 8×32-bit) and synchronized triple SAR ADCs (12-bit, 1 Msps, 67 total channels) enable motor-sense and closed-loop body control functions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, with hardware IPC and independent MPUs |
| Memory | 2112-KB code-flash (RWW, dual-bank for FOTA), 128-KB work-flash, 256-KB SRAM with configurable retention |
| Crypto Engine | HSM-compliant: AES-128/192/256, SHA-256/512, ECC/RSA, TRNG/PRNG, GCM mode, eSHE secure boot |
| Automotive Safety | ASIL-B compliant: SECDED ECC on flash/SRAM, SMPU, PPU, MCWDT, CSV, LVD/BOD/OVD monitoring |
| Communication | 8× CAN FD (ISO 11898-1:2015, up to 8 Mbps), 12× LIN (ISO 17987), 4× CXPI (20 kbps), 8× SCB (I²C/SPI/UART) |
| Analog & Timing | 3× SAR ADC (12-bit, 1 Msps, 67 ch), 75×16-bit + 8×32-bit TCPWM, 11× EVTGEN timers, RTC with leap-year correction |
| Package & Environment | 176-LQFP (24×24×1.7 mm, 0.5-mm pitch), AEC-Q100 Grade 2 (–40°C to +105°C), 2.7–5.5-V operation |
Pinout & Package
176-pin LQFP package (24 mm × 24 mm, 0.5 mm pitch, 1.7 mm max height) with dedicated power/ground distribution, multiple VDDD/VDDA/VCCD rails, and segregated analog/digital I/O banks. Pin assignments include 152 GPIOs (GPIO_STD/GPIO_ENH), 8 CAN FD transceiver pins (TX/RX per channel), 12 LIN TX pins, 4 CXPI pins, 3 crystal oscillator inputs (ECO/WCO), JTAG/SWD debug interface, and dedicated reset/programming pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDD_0–VDDD_7 | Digital core supply (1.1 V) | Eight independent 1.1-V core power domains for voltage domain partitioning and fault containment |
| VDDA_0–VDDA_2 | Analog supply (2.7–5.5 V) | Three isolated analog supplies supporting SAR ADC reference stability and noise immunity |
| P0[0]–P0[7] | GPIO_STD bank 0 | Configurable as CAN FD0_TX/RX, LIN0_TX, SCB0_I2C_SDA/SCL, or general-purpose I/O with slew-rate control |
| P12[0]–P12[7] | GPIO_ENH bank 12 | Supports high-speed PWM output, quadrature encoder input, and event-triggered ADC sampling for motor control |
| TCK/TMS/TDO/TDI/nTRST | JTAG debug interface | IEEE-1149.1-compliant boundary scan and full-core debugging; SWD alternative available on TCK/SWDIO pins |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Security Partitioning | M0+ handles secure boot, crypto operations, and peripheral arbitration-preventing M4F software faults from compromising HSM or eSHE keys |
| Firmware Update Over-The-Air (FOTA) | Dual-bank flash enables atomic firmware swap with rollback; RWW allows background update while executing active application |
| Synchronized Triple ADC Sampling | Simultaneous start of all three SAR ADCs enables precise phase-current capture in 3-phase motor control without software coordination |
| Hardware Event Generator (EVTGEN) | 11 independent timers trigger wakeup, ADC conversion, or interrupt handling directly from DeepSleep-eliminating polling overhead |
| Smart I/O Logic Blocks | Five programmable logic units perform Boolean combinations (AND/OR/XOR) on up to 36 GPIO_STD pins-reducing MCU load for signal conditioning |
Applications
| Body Control Module (BCM) | Roof Module Control |
|---|---|
|
Use Scenario: Centralized control of door locks, window lifts, lighting, and seat position memory in premium vehicles. IC Role / Device Role / Timing Role: Primary controller running AUTOSAR-compliant BSW stack; M4F executes application layer, M0+ manages CAN FD/LIN comms and secure key storage. Use Value: Dual-core isolation ensures LIN timeout responses remain deterministic even during CAN FD firmware updates or crypto key generation. |
Use Scenario: Integrated sunroof, panoramic roof, and ambient lighting control with gesture sensing and thermal monitoring. IC Role / Device Role / Timing Role: Real-time coordinator of motor drivers (via TCPWM), capacitive touch inputs, and RGB LED dimming (via PWM_DT); RTC synchronizes lighting schedules. Use Value: Synchronized ADC sampling captures thermistor and photodiode readings simultaneously for adaptive brightness control without CPU intervention. |
| Front-End Domain Controller | Electronic Parking Brake (EPB) |
|
Use Scenario: Aggregation of radar, camera, and ultrasonic sensor data for ADAS pre-processing before forwarding to central domain controller. IC Role / Device Role / Timing Role: Edge preprocessing node using M4F for sensor fusion algorithms; M0+ secures CAN FD message signing and validates firmware integrity. Use Value: Hardware crypto engine accelerates ECDSA signature verification for signed sensor metadata-meeting ISO/SAE 21434 cybersecurity requirements. |
Use Scenario: Fail-operational parking brake actuation with redundant motor control, force feedback, and emergency release logic. IC Role / Device Role / Timing Role: Safety-critical controller implementing ASIL-B motor commutation (via TCPWM dead-time), torque monitoring (via ADC), and watchdog supervision (MCWDT + CSV). Use Value: SECDED ECC on SRAM and flash prevents silent data corruption in brake hold state variables-validated per ISO 26262 clause 8.4.3. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP S32K344 | Single-core Arm® Cortex®-M7 (320 MHz), no M0+ companion core; includes ASIL-D capable lockstep cores and Ethernet MAC | Better suited for gateway or high-throughput ADAS preprocessing; lacks native CXPI and Smart I/O logic blocks | Select when Ethernet connectivity or lockstep redundancy is required over dual-core asymmetric partitioning |
| Renesas RH850/U2A | 32-bit RH850 core (240 MHz), no FPU or crypto accelerator; supports CAN FD and LIN but no CXPI or hardware ADC synchronization | Stronger legacy toolchain support for Japanese OEMs; limited secure boot capability (no eSHE/HSM) | Select for cost-sensitive body electronics where advanced crypto and FOTA are not mandated |
Compared with NXP S32K344 and Renesas RH850/U2A, CYT2B94BACQ0AZSGST uniquely combines M4F+M0+ asymmetric processing, CXPI support for next-gen vehicle networks, and hardware-synchronized triple ADCs-making it optimal for safety-aware, feature-rich body domain controllers requiring both real-time responsiveness and robust security.
Availability
CYT2B94BACQ0AZSGST is available at Aetrix Electronics and suitable for body control modules, roof modules, front-end domain controllers, and electronic parking brake systems requiring stable component supply, AEC-Q100 Grade 2 qualification, and long-term automotive lifecycle support.
Supply support for CYT2B94BACQ0AZSGST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global R&D centers and automotive-grade wafer fabs.
This part belongs to the TRAVEO™ T2G family-designed specifically for automotive body electronics requiring functional safety (ASIL-B), secure communication (CAN FD/LIN/CXPI), and heterogeneous processing for real-time control plus security offload.
FAQ
What is the maximum operating temperature range for CYT2B94BACQ0AZSGST?
CYT2B94BACQ0AZSGST is qualified per AEC-Q100 Grade 2, supporting continuous operation from –40°C to +105°C ambient temperature. This rating applies to the full 176-LQFP package under specified voltage (2.7–5.5 V) and thermal derating conditions defined in Section 27.2 of the datasheet.
Does CYT2B94BACQ0AZSGST support hardware-based secure boot with public-key verification?
Yes-it implements eSHE-compliant secure boot using RSA/ECC digital signature verification. The crypto engine performs SHA-256 hashing and ECDSA/RSA signature validation on boot images stored in flash, with keys protected in tamper-resistant HSM memory and enforced by the M0+ subsystem.
How many CAN FD channels are physically implemented and what is their maximum data rate?
The device integrates eight fully independent CAN FD controllers. Each supports bit rates up to 8 Mbps in the data phase (per ISO 11898-1:2015), subject to external transceiver and physical layer limitations. All eight channels operate concurrently with separate TX/RX pins and dedicated message RAM.
Is the 176-LQFP package lead-free and RoHS-compliant?
Yes-CYT2B94BACQ0AZSGST uses a lead-free, halogen-free, RoHS-compliant 176-LQFP package (JEDEC MS-026, Pb-free plating). Compliance is documented in Infineon's Material Declaration (MD-00022825) and certified to EU RoHS Directive 2011/65/EU Annex II.
CYT2B94BACQ0AZSGST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 80-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 63
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 52x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B94BACQ0AZSGST FAQ
1.How can I place an order for CYT2B94BACQ0AZSGST through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B94BACQ0AZSGST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B94BACQ0AZSGST reliable?
The price and inventory of CYT2B94BACQ0AZSGST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B94BACQ0AZSGST is usually 5 days.
3.What payment methods are accepted for CYT2B94BACQ0AZSGST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B94BACQ0AZSGST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B94BACQ0AZSGST?
CYT2B94BACQ0AZSGST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B94BACQ0AZSGST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B94BACQ0AZSGST?
For technical support, including CYT2B94BACQ0AZSGST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B94BACQ0AZSGST requirements.
6.How does Aetrix verify that CYT2B94BACQ0AZSGST is sourced from the original manufacturer or authorized distributors?
All CYT2B94BACQ0AZSGST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B94BACQ0AZSGST meets industry standards.
7.What is the process for return or replacement of CYT2B94BACQ0AZSGST?
All CYT2B94BACQ0AZSGST units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B94BACQ0AZSGST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B94BACQ0AZSGST part is unused and in its original packaging.
Return procedure for CYT2B94BACQ0AZSGST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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