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Infineon Technologies CYT2B95BACQ0AZEGS
- Part No.:
- CYT2B95BACQ0AZEGS
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
CYT2B95BACQ0AZEGS.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 100QFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,445
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Product details
Overview
CYT2B95BACQ0AZEGS from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112 KB code-flash with RWW support, 256 KB SRAM, and integrated CAN FD (up to 8 channels), LIN (up to 12 channels), and CXPI (up to 4 channels). It targets body control modules requiring ASIL-B functional safety, secure boot, and hardware crypto acceleration (AES-128/192/256, SHA-256/512, ECC, TRNG).
For engineers reviewing the CYT2B95BACQ0AZEGS datasheet, CYT2B95BACQ0AZEGS pinout, CYT2B95BACQ0AZEGS application, or CYT2B95BACQ0AZEGS equivalent, this part delivers deterministic real-time control, hardware-enforced security partitioning between M4F and M0+, and fine-grained low-power modes (Hibernate, DeepSleep) with multi-pin wakeup-critical for automotive ECU power budgeting and OTA firmware updates.
Technical Context
The CYT2B95BACQ0AZEGS implements a tightly coupled dual-CPU architecture: the M4F handles primary application logic and motor control via 75×16-bit + 8×32-bit TCPWM blocks, while the M0+ manages peripheral offload, security services (eSHE/HSM), and watchdog supervision. Inter-processor communication occurs through dedicated hardware mailboxes and shared memory protected by SMPU.
Its clock system integrates IMO, ILO, ECO, WCO, PLL, and FLL sources, enabling dynamic frequency scaling across operating modes. Safety-critical memories employ SECDED ECC, and all peripherals-including CAN FD controllers compliant with ISO 11898-1:2015 and ISO 16845:2015-are protected by PPU and MPU enforcement.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, with hardware mailbox IPC and independent MPUs |
| Memory | 2112 KB code-flash (RWW-capable, dual-bank for FOTA), 128 KB work-flash, 256 KB SRAM with configurable retention |
| CAN FD Channels | 8 runtime-configurable channels supporting up to 8 Mbps data rate per channel, ISO 11898-1:2015 compliant |
| LIN Channels | 12 independent LIN controllers compliant with ISO 17987, supporting slave/master roles and auto-baud detection |
| Crypto Engine | HSM-accelerated AES-128/192/256, SHA-256/512, ECC, RSA, TRNG, and GCM mode-enabling secure boot and OTA authentication |
| Functional Safety | ASIL-B compliant with SECDED ECC on flash/SRAM, SMPU, PPU, dual BOD thresholds (2.7 V / 3.0 V on VDDD/VDDA), and MCWDT |
| I/O Count | 152 programmable GPIOs (GPIO_STD/GPIO_ENH), with up to 152 pins supporting wakeup from Sleep modes |
Pinout & Package
CYT2B95BACQ0AZEGS is packaged in a 176-pin LQFP (24 × 24 × 1.7 mm, 0.5-mm pitch) with dedicated power, ground, analog reference, debug (SWD/JTAG), and high-speed peripheral pins including CAN FD TX/RX, LIN TX, CXPI, and multiple ADC input channels.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDD / VDDA | Core & Analog Supply | 2.7–5.5 V main supply; VDDA powers SAR ADCs and references-requires separate filtering for noise-sensitive measurements |
| P0[0]–P0[7] | GPIO_STD Bank 0 | Configurable digital I/Os supporting wakeup, event generation, and Smart I/O Boolean logic operations |
| CANFD0_TX / CANFD0_RX | CAN FD Channel 0 Interface | Differential pair for CAN FD physical layer connection; requires external transceiver and termination |
| LIN0_TX | LIN Channel 0 Transmit | Open-drain output driving LIN bus; supports automatic baud rate detection and sleep/wakeup framing |
| SWDIO / SWCLK | Serial Wire Debug Interface | Two-pin debug interface supporting full JTAG/SWD access, ETM trace, and secure programming via SWD |
| ADC0_IN0–ADC0_IN23 | SAR ADC0 Input Channels | 24 logical inputs mapped to 25 physical pins; supports synchronized sampling with ADC1/ADC2 for motor current sensing |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Security Partitioning | M0+ enforces secure boot, key management, and crypto services; M4F runs application code-hardware-isolated via SMPU and mailbox |
| Firmware Update Support | Dual-bank flash enables atomic over-the-air (FOTA) updates without runtime interruption; RWW allows concurrent execution and reprogramming |
| Low-Power Wakeup Flexibility | Hibernate mode wakeup via 2 dedicated pins; Sleep mode wakeup via any of 152 GPIOs; DeepSleep wakeup via EVTGEN timers or RTC alarms |
| Motor Control Integration | 75×16-bit + 8×32-bit TCPWM blocks with dead-time insertion, quadrature decoding, and synchronized ADC triggering for BLDC/PMSM control |
| Peripheral Reconfigurability | 8 SCB units each configurable as UART/I2C/SPI; 12 LIN controllers; 4 CXPI interfaces-all runtime-reconfigurable without reset |
Applications
| Body Control Module (BCM) | Roof Module Controller |
|---|---|
|
Use Scenario: Centralized control of door locks, window lifts, lighting, and seat position memory in modern vehicles. IC Role / Device Role / Timing Role: Primary MCU executing real-time CAN FD messaging, LIN slave coordination, and PWM-driven motor actuation. Use Value: Dual-core separation ensures safety-critical lock/unlock logic runs independently on M0+, while M4F handles complex lighting animations and diagnostics-meeting ASIL-B requirements. |
Use Scenario: Integrated control of sunroof, panoramic roof panels, interior ambient lighting, and rain sensors. IC Role / Device Role / Timing Role: Real-time coordinator of LIN-connected actuators and CAN FD-linked gateway messages, with precise PWM timing for smooth glass movement. Use Value: 75×16-bit TCPWM blocks enable synchronized multi-axis motion control; 12-bit SAR ADCs monitor rain sensor capacitance and light intensity with 1 Msps sampling. |
| Smart Junction Box (SJB) | Electronic Parking Brake (EPB) |
|
Use Scenario: Power distribution and load switching for chassis electronics, including fuse monitoring and short-circuit protection. IC Role / Device Role / Timing Role: High-integrity supervisor managing CAN FD fault reporting, GPIO-based relay control, and voltage/current monitoring via SAR ADCs. Use Value: SECDED ECC on flash/SRAM and dual BOD thresholds ensure reliable operation during battery transients; PPU prevents unauthorized peripheral access. |
Use Scenario: Fail-operational braking actuation with redundant motor control, force feedback, and parking position verification. IC Role / Device Role / Timing Role: Safety-certified controller executing torque control loops, CAN FD brake status exchange, and secure motor driver gate sequencing. Use Value: Hardware crypto engine validates signed firmware updates; synchronized triple ADC sampling verifies motor current, voltage, and temperature for torque estimation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP S32K344 | Single-core Arm® Cortex®-M7 (320 MHz); no M0+ companion core; includes HSE security module but lacks integrated CXPI | Targets higher-performance gateway/ADAS domains; less optimized for LIN/CXPI-rich body electronics | Prefer when higher single-thread compute throughput is required and CXPI is not needed. |
| Renesas RH850/U2A | 32-bit RXv3 core (240 MHz); proprietary ISA; supports CAN FD and LIN but no native crypto accelerator or RWW flash | Used in powertrain and chassis ECUs; requires external secure element for HSM-level security | Choose where legacy RH850 toolchain compatibility and ASIL-D certification path are mandatory. |
Compared with NXP S32K344 and Renesas RH850/U2A, CYT2B95BACQ0AZEGS uniquely combines dual-core deterministic partitioning, native CXPI support, RWW flash for seamless FOTA, and on-die HSM-making it optimal for cost-sensitive, feature-rich automotive body domain controllers requiring ASIL-B compliance without external security components.
Availability
CYT2B95BACQ0AZEGS is available at Aetrix Electronics and suitable for automotive body control modules, smart junction boxes, roof module controllers, and electronic parking brake systems requiring stable component supply, long lifecycle assurance, and ASIL-B-compliant silicon.
Supply support for CYT2B95BACQ0AZEGS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with leadership in automotive microcontrollers and power semiconductors.
CYT2B95BACQ0AZEGS belongs to the TRAVEO™ T2G family, designed specifically for automotive body electronics requiring dual-core real-time processing, integrated CAN FD/LIN/CXPI, hardware security, and functional safety up to ASIL-B.
FAQ
What is the maximum operating frequency of the Cortex-M4F core in CYT2B95BACQ0AZEGS?
The Arm® Cortex®-M4F core operates at a maximum frequency of 160 MHz, as confirmed in the device's electrical specifications and clock diagram sections of the official Infineon datasheet (Rev. *I, p.21, p.136). This frequency is achievable under specified voltage (2.7–5.5 V) and temperature conditions, and supports single-cycle multiply and single-precision FPU operations without throttling.
Does CYT2B95BACQ0AZEGS support Over-The-Air (OTA) firmware updates?
Yes-CYT2B95BACQ0AZEGS supports secure OTA updates via its dual-bank flash architecture and Read-While-Write (RWW) capability. The 2112 KB code-flash is divided into independently erasable banks, allowing background programming of one bank while executing from the other, enabling atomic, fail-safe firmware swaps without system reset or downtime.
How many CAN FD channels does CYT2B95BACQ0AZEGS support, and what is their data rate limit?
CYT2B95BACQ0AZEGS supports up to eight CAN FD channels, each capable of data rates up to 8 Mbps, as stated in the features list (p.3) and AC specifications (p.112) of the Infineon datasheet. The actual achievable rate depends on physical layer topology and external transceiver performance, but the controller complies fully with ISO 11898-1:2015 and Bosch CAN FD v1.0 specifications.
Is hardware cryptographic acceleration included, and which algorithms are supported?
Yes-CYT2B95BACQ0AZEGS includes a dedicated hardware crypto engine supporting AES-128/192/256, SHA-256/512, ECC, RSA, 3DES, CRC16/32, TRNG, and Galois/Counter Mode (GCM). These capabilities are documented in the "Crypto engine" section (p.2) and verified in the ordering information footnote confirming HSM availability for this MPN.
CYT2B95BACQ0AZEGS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 100-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 57x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B95BACQ0AZEGS FAQ
1.How can I place an order for CYT2B95BACQ0AZEGS through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B95BACQ0AZEGS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B95BACQ0AZEGS reliable?
The price and inventory of CYT2B95BACQ0AZEGS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B95BACQ0AZEGS is usually 5 days.
3.What payment methods are accepted for CYT2B95BACQ0AZEGS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B95BACQ0AZEGS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B95BACQ0AZEGS?
CYT2B95BACQ0AZEGS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B95BACQ0AZEGS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B95BACQ0AZEGS?
For technical support, including CYT2B95BACQ0AZEGS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B95BACQ0AZEGS requirements.
6.How does Aetrix verify that CYT2B95BACQ0AZEGS is sourced from the original manufacturer or authorized distributors?
All CYT2B95BACQ0AZEGS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B95BACQ0AZEGS meets industry standards.
7.What is the process for return or replacement of CYT2B95BACQ0AZEGS?
All CYT2B95BACQ0AZEGS units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B95BACQ0AZEGS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B95BACQ0AZEGS part is unused and in its original packaging.
Return procedure for CYT2B95BACQ0AZEGS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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