My Inquiry
My Account
Infineon Technologies CYT2B95BACQ0AZEGST
- Part No.:
- CYT2B95BACQ0AZEGST
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
CYT2B95BACQ0AZEGST.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 100QFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,730
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CYT2B95BACQ0AZEGST from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112 KB code-flash with RWW support, 256 KB SRAM, and integrated CAN FD (up to 8 channels), LIN (up to 12 channels), and CXPI (up to 4 channels). It targets body control modules requiring ASIL-B functional safety, secure boot, and hardware crypto acceleration including AES-128/192/256, SHA-256/512, and ECC.
For engineers reviewing the CYT2B95BACQ0AZEGST datasheet, CYT2B95BACQ0AZEGST pinout, CYT2B95BACQ0AZEGST application, or CYT2B95BACQ0AZEGST equivalent, this part supports fine-grained power management across Hibernate/Sleep/DeepSleep modes, synchronized multi-ADC sampling for motor sensing, hardware inter-processor communication, and SWD/JTAG debug with ETM trace - all in a 176-LQFP package rated for automotive temperature range.
Technical Context
The CYT2B95BACQ0AZEGST implements a tightly coupled dual-CPU architecture: the M4F handles real-time application processing with FPU and MPU, while the M0+ offloads peripheral control, security services (eSHE/HSM), and watchdog supervision. Hardware IPC and three independent DMA controllers (P-DMA0: 92 ch, P-DMA1: 44 ch, M-DMA0: 4 ch) enable deterministic data movement without CPU intervention.
Its safety architecture includes SECDED ECC on flash and SRAM, SMPU for shared memory protection, PPU for peripheral access control, and dual-threshold BOD (2.7 V / 3.0 V on VDDD/VDDA; 1.1 V on VCCD). Clocking relies on IMO/ILO/ECO/WCO sources with PLL/FLL synthesis, supporting precise timing for CAN FD (up to 8 Mbps) and LIN (ISO 17987-compliant) operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, with hardware IPC and separate MPUs |
| Memory | 2112 KB code-flash (RWW-capable, dual-bank for FOTA), 128 KB work-flash, 256 KB SRAM with selectable retention |
| Crypto Engine | HSM-compliant with AES-128/192/256, SHA-256/512, ECC, RSA, TRNG/PRNG, and Galois/Counter Mode (GCM) |
| Automotive Interfaces | 8× CAN FD (ISO 11898-1:2015, ISO 16845-certified), 12× LIN (ISO 17987), 4× CXPI (20 kbps) |
| Analog Peripherals | 3× SAR ADCs (12-bit, 1 Msps each), 67 total external channels, synchronized sampling, internal temp/bandgap monitoring |
| Power & Safety | ASIL-B compliant; SECDED ECC on flash/SRAM; SMPU/PPU; dual-threshold BOD; Hibernate/Sleep/DeepSleep modes |
| Package | 176-pin LQFP (24 × 24 × 1.7 mm, 0.5-mm pitch), automotive-grade (-40°C to +125°C) |
Pinout & Package
CYT2B95BACQ0AZEGST is housed in a 176-pin LQFP package (24 mm × 24 mm, 0.5 mm pitch, 1.7 mm max height) optimized for automotive PCB layout and thermal dissipation under extended temperature operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDD, VDDA, VCCD, VSS | Power supply and ground rails | Dedicated domains: VDDD/VSS for digital core (1.1 V), VDDA/VSSA for analog (2.7–5.5 V), VCCD for deep-sleep regulator input |
| P0[0]–P0[7], P1[0]–P1[7], ..., P10[0]–P10[7] | GPIO_STD / GPIO_ENH I/O banks | 152 total programmable pins; GPIO_ENH supports Smart I/O Boolean logic and event-triggered wakeup from Sleep/DeepSleep |
| CANFD0_TX/RX – CANFD7_TX/RX | CAN FD transceiver interface | Eight differential CAN FD channels with configurable bit timing, supporting up to 8 Mbps and ISO 11898-1:2015 compliance |
| LIN0–LIN11 | LIN bus physical layer interface | Twelve dedicated LIN channels compliant with ISO 17987; each supports auto-baud detection and slave node response handling |
| CXPI0–CXPI3 | CXPI bus interface | Four CXPI channels (20 kbps) for low-cost vehicle network communication; supports master/slave roles and error detection |
| TCK, TMS, TDO, TDI, nTRST, SWDIO, SWCLK | JTAG/SWD debug interface | Fully compliant IEEE-1149.1 JTAG and Arm® SWD; enables flash programming, real-time debugging, and ETM instruction/data trace |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Security Partitioning | M4F runs application firmware; M0+ isolates security-critical tasks (secure boot, crypto, HSM), enforced by hardware IPC and SMPU |
| Firmware Update Over-The-Air (FOTA) | Dual-bank flash architecture enables atomic firmware swap with zero downtime and rollback capability during field updates |
| Synchronized Motor Sensing | Three SAR ADCs support simultaneous sampling across all 67 channels, enabling precise rotor position estimation in BLDC/PMSM drives |
| Low-Power Wakeup Flexibility | Up to 152 GPIOs can wake from Sleep mode; two dedicated pins + RTC/EVTGEN timers support wakeup from Hibernate/DeepSleep |
| Functional Safety Infrastructure | MPU/SMPU/PPU, SECDED ECC, dual-threshold BOD, and clock supervisor (CSV) collectively satisfy ASIL-B requirements per ISO 26262 |
Applications
| Body Control Module (BCM) | Door Module Control |
|---|---|
|
Use Scenario: Centralized control of lighting, windows, locks, mirrors, and seat functions in modern vehicles. IC Role / Device Role / Timing Role: Primary MCU managing LIN/CAN FD gatewaying, PWM dimming, and secure keyless entry authentication. Use Value: Dual-core separation ensures real-time window lift control (M4F) while M0+ handles AES-encrypted RF signal validation and secure boot integrity checks. |
Use Scenario: Integrated control of power windows, door locks, side mirrors, and interior lighting within a single door ECU. IC Role / Device Role / Timing Role: Real-time motor control via TCPWM blocks and synchronized ADC sampling for anti-pinch detection. Use Value: 75× 16-bit TCPWM timers with dead-time insertion and 3× synchronized SAR ADCs enable precise brushless motor commutation and force feedback sensing. |
| Roof Module (Sunroof/Blind Control) | Smart Junction Box (SJB) |
|
Use Scenario: Position-aware sunroof and roller blind actuation with obstacle detection and smooth motion profiling. IC Role / Device Role / Timing Role: Sensor fusion hub aggregating Hall effect, current sense, and potentiometer inputs via GPIO_ENH and Smart I/O logic. Use Value: Smart I/O blocks perform real-time Boolean logic on sensor signals (e.g., AND of current spike + position limit) to trigger immediate motor stop without CPU latency. |
Use Scenario: Power distribution and load switching for multiple vehicle subsystems (lighting, HVAC, infotainment) with diagnostics and protection. IC Role / Device Role / Timing Role: High-integration MCU managing CAN FD communication, load driver control, and voltage/current monitoring via SAR ADCs. Use Value: 8× CAN FD channels allow concurrent communication with engine, chassis, and infotainment domains; 256 KB SRAM supports complex diagnostic logging and fault history storage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP S32K344 | Single 240-MHz Arm® Cortex®-M7 core; no companion M0+; includes ASIL-D capable lockstep cores and Ethernet MAC | Better suited for high-end gateway or domain controller roles requiring Ethernet or lockstep redundancy; lacks native CXPI and Smart I/O | Select when Ethernet connectivity or ASIL-D functional safety is required; not drop-in for LIN/CXPI-heavy BCM designs |
| Renesas RH850/U2A | 32-bit RH850 core (not Arm); 200-MHz max; 2 MB flash; supports CAN FD/LIN but no hardware crypto accelerator or Smart I/O | Strong legacy automotive adoption; requires external crypto IC for secure boot; limited low-power flexibility vs. DeepSleep/Hibernate modes | Prefer where toolchain continuity with existing RH850-based platforms exists; avoid if hardware-accelerated ECC/AES or ultra-low-power sleep modes are critical |
Compared with NXP S32K344 and Renesas RH850/U2A, CYT2B95BACQ0AZEGST uniquely combines dual-Arm cores with hardware Smart I/O, CXPI support, and granular power-state control - making it optimal for cost-sensitive, feature-rich body electronics where LIN/CAN FD coexistence and secure FOTA are mandatory.
Availability
CYT2B95BACQ0AZEGST is available at Aetrix Electronics and suitable for body control modules, door modules, roof modules, and smart junction boxes requiring stable component supply across automotive production lifecycles.
Supply support for CYT2B95BACQ0AZEGST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and security solutions, with leadership in silicon carbide, radar, and automotive MCUs.
CYT2B95BACQ0AZEGST belongs to the TRAVEO™ T2G family - designed specifically for automotive body electronics requiring functional safety (ASIL-B), secure firmware execution, and mixed-signal integration in compact LQFP packages.
FAQ
What is the maximum operating frequency of each CPU core in CYT2B95BACQ0AZEGST?
The CYT2B95BACQ0AZEGST integrates a 160-MHz Arm® Cortex®-M4F core for primary application processing and a 100-MHz Arm® Cortex®-M0+ core dedicated to peripheral management and security functions. Both cores operate independently with their own clock domains and memory protection units, enabling deterministic real-time performance and hardware-enforced isolation.
Does CYT2B95BACQ0AZEGST support over-the-air (OTA) firmware updates?
Yes - CYT2B95BACQ0AZEGST supports robust OTA updates via its dual-bank flash architecture (2112 KB code-flash), Read-While-Write capability, and hardware-assisted secure boot. The M0+ core validates digital signatures using ECDSA before executing new firmware, ensuring authenticated, atomic, and rollback-safe updates without interrupting vehicle operation.
How many CAN FD channels does CYT2B95BACQ0AZEGST support, and what is the maximum data rate?
CYT2B95BACQ0AZEGST supports up to eight CAN FD channels compliant with ISO 11898-1:2015 and certified to ISO 16845:2015. Each channel achieves up to 8 Mbps data phase rates, subject to physical layer constraints (transceiver and cabling). Bit timing is fully configurable per channel via dedicated registers in the CAN FD IP block.
What safety certifications apply to CYT2B95BACQ0AZEGST for automotive use?
CYT2B95BACQ0AZEGST is designed to meet ASIL-B requirements per ISO 26262:2018. Its safety features include SECDED ECC on flash and SRAM, Shared Memory Protection Unit (SMPU), Peripheral Protection Unit (PPU), dual-threshold Brown-Out Detection, Clock Supervision, and hardware error correction - all documented in Infineon's Functional Safety Manual (FSM) for TRAVEO™ T2G.
CYT2B95BACQ0AZEGST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 100-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 57x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B95BACQ0AZEGST FAQ
1.How can I place an order for CYT2B95BACQ0AZEGST through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B95BACQ0AZEGST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B95BACQ0AZEGST reliable?
The price and inventory of CYT2B95BACQ0AZEGST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B95BACQ0AZEGST is usually 5 days.
3.What payment methods are accepted for CYT2B95BACQ0AZEGST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B95BACQ0AZEGST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B95BACQ0AZEGST?
CYT2B95BACQ0AZEGST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B95BACQ0AZEGST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B95BACQ0AZEGST?
For technical support, including CYT2B95BACQ0AZEGST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B95BACQ0AZEGST requirements.
6.How does Aetrix verify that CYT2B95BACQ0AZEGST is sourced from the original manufacturer or authorized distributors?
All CYT2B95BACQ0AZEGST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B95BACQ0AZEGST meets industry standards.
7.What is the process for return or replacement of CYT2B95BACQ0AZEGST?
All CYT2B95BACQ0AZEGST units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B95BACQ0AZEGST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B95BACQ0AZEGST part is unused and in its original packaging.
Return procedure for CYT2B95BACQ0AZEGST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CYT2B95BACQ0AZEGST Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…
Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…
A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…
Engineering guide to Raspberry Pi alternatives, covering chip-level differences, Orange Pi, ROCK, Jetson, Banana Pi, NanoPi, Compute Module, Pico, GPIO, camera, HAT compatibility, and replacement risks…
Engineering guide to dynamic load response testing for high-current buck converters, covering load step setup, slew rate, Vcore undershoot, overshoot, recovery time, probe location, output capacitors a…
Engineering guide to output capacitor selection for ASIC Vcore rails, covering bulk capacitors, polymer capacitors, MLCC decoupling, DC bias, ESR, ESL, placement, transient response and substitution ri…
Engineering guide to high-current ASIC Vcore rails, covering 12-phase buck architecture, PMBus control, dynamic load testing, output capacitor networks, smart power stage selection, thermal design and …
Voltage regulator guide covering linear, LDO, 7805, Zener, adjustable, buck, VRM and alternator regulators, with design checks, testing methods, troubleshooting and datasheet-based selection.
