Infineon Technologies CYT2B95BACQ0AZSGST
- Part No.:
- CYT2B95BACQ0AZSGST
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
CYT2B95BACQ0AZSGST.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 100QFP
- Quantity:
- Payment:

- Shipping:

Inventory:500
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Product details
Overview
CYT2B95BACQ0AZSGST from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112-KB code-flash with RWW support, 256-KB SRAM, and integrated CAN FD (up to 8 channels), LIN (up to 12 channels), and CXPI (up to 4 channels). It targets body control modules requiring ASIL-B functional safety, secure boot via eSHE/HSM, and low-power operation from 2.7 V to 5.5 V.
For engineers reviewing the CYT2B95BACQ0AZSGST datasheet, CYT2B95BACQ0AZSGST pinout, CYT2B95BACQ0AZSGST application, or CYT2B95BACQ0AZSGST equivalent, this part supports hardware inter-processor communication, SECDED ECC on flash/SRAM, synchronized SAR ADC sampling for motor sensing, and runtime-reconfigurable SCB interfaces for I²C/SPI/UART - critical for automotive ECU design and FOTA-capable systems.
Technical Context
The CYT2B95BACQ0AZSGST implements a tightly coupled dual-CPU architecture: the M4F handles primary real-time control and floating-point computation, while the M0+ manages peripheral offload, security services (eSHE/HSM), and safe interrupt handling. Hardware IPC includes dedicated mailbox registers and event-triggered synchronization.
Its safety architecture integrates MPU, SMPU, PPU, SECDED ECC on all safety-critical memories, and dual-threshold BOD (2.7 V / 3.0 V on VDDD/VDDA; 1.1 V on VCCD), meeting ASIL-B requirements per ISO 26262. Clock supervision includes CSV, FLL, PLL, IMO, ILO, ECO, and WCO sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, enabling real-time control and secure peripheral management |
| Flash Memory | 2112-KB code-flash + 128-KB work-flash with Read-While-Write (RWW) and dual-bank FOTA support |
| SRAM | 256-KB with selectable retention granularity for low-power mode optimization |
| CAN FD Channels | Up to 8 channels compliant with ISO 11898-1:2015 and Bosch CAN FD v1.0, supporting up to 8 Mbps data rate |
| ADC System | Three 12-bit SAR ADCs (ADC0–ADC2) with up to 67 external channels and synchronized sampling for motor-sense applications |
| Security Engine | HSM-compliant crypto engine with AES-128/192/256, SHA-256/512, RSA/ECC, TRNG, and GCM mode |
| Functional Safety | ASIL-B certified with MPU, SMPU, PPU, SECDED ECC on flash/SRAM, and multi-level BOD |
Pinout & Package
Package: 176-pin LQFP (24 × 24 × 1.7 mm, 0.5-mm pitch), RoHS-compliant, automotive-grade AEC-Q100 qualified.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDD, VDDA, VCCD | Power supply inputs | VDDD/VDDA: 2.7–5.5 V digital/analog core supply; VCCD: 1.1 V internal core regulator output |
| P0[0]–P0[7], P1[0]–P1[7], etc. | GPIO banks (up to 152 total) | Configurable as GPIO_STD or GPIO_ENH; support wakeup from Sleep/DeepSleep/Hibernate modes |
| CANFD0_TX, CANFD0_RX, … CANFD7_RX | CAN FD transceiver interface | Dedicated differential pairs per channel; each supports ISO 11898-1:2015 and non-ISO CAN FD v1.0 |
| SCB0_I2C_SDA, SCB0_SPI_MOSI, SCB0_UART_RX | Multi-function serial interface pins | Runtime-reconfigurable per SCB block (8 total); support I²C/SPI/UART protocols simultaneously |
| ADC0_IN0–ADC0_IN23, ADC1_IN0–ADC1_IN31, ADC2_IN0–ADC2_IN7 | Analog input channels | 67 total external analog inputs mapped across three SAR ADCs with sequencer and autonomous scanning |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Hardware IPC | Mailbox-based inter-processor communication with event-triggered synchronization and shared memory protection |
| FOTA-Ready Flash Architecture | Dual-bank flash with RWW enables seamless firmware updates without halting application execution |
| Synchronized Multi-ADC Sampling | Simultaneous start of conversion across ADC0–ADC2 for precise motor current/voltage phase alignment |
| ASIL-B Safety Subsystem | Integrated SMPU, PPU, SECDED ECC, and dual-threshold BOD ensure memory/data integrity in automotive environments |
| Runtime-Reconfigurable SCBs | 8 serial communication blocks dynamically assignable as I²C, SPI, or UART-reducing BOM count and PCB routing complexity |
Applications
| Body Control Module (BCM) | Door Module Controller |
|---|---|
Use Scenario: Centralized control of lighting, windows, locks, and mirrors in modern vehicle door assemblies. IC Role / Device Role / Timing Role: Primary MCU executing LIN slave protocol for door node communication and PWM-driven motor control for window lift. Use Value: 12-channel LIN support enables daisy-chained multi-node topology; synchronized ADC sampling ensures accurate current sensing for anti-pinch detection. | Use Scenario: Integrated control unit managing power distribution, sensor fusion (door open/close, impact detection), and CAN FD gateway functions within a single door module. IC Role / Device Role / Timing Role: Dual-core coordination: M4F runs real-time motor control and sensor processing; M0+ handles LIN/CXPI messaging and secure boot verification. Use Value: Hardware crypto engine enables authenticated firmware updates over CAN FD; ASIL-B safety features satisfy OEM functional safety requirements. |
| Roof Module Controller | Seat Control Unit |
Use Scenario: Smart roof module managing sunroof actuation, ambient lighting, and rain sensor integration in premium vehicles. IC Role / Device Role / Timing Role: Real-time TCPWM generation for smooth sunroof motor control; SAR ADC monitoring of rain sensor voltage and temperature-compensated LED dimming. Use Value: 75× 16-bit TCPWM blocks provide fine-grained timing resolution; programmable analog supports direct sensor interface without external signal conditioning. | Use Scenario: Seat ECU controlling position motors, heating elements, and occupant detection sensors (capacitive or pressure-based). IC Role / Device Role / Timing Role: Secure boot and HSM-managed key storage protect seat calibration data; synchronized ADC sampling captures simultaneous seat rail and backrest position feedback. Use Value: eSHE-compliant secure boot prevents unauthorized firmware modification; 256-KB SRAM with retention granularity preserves seat position profiles during ignition-off states. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TC377TP-64F200N AC | TriCore™ architecture (not Arm), 200-MHz CPU, 4-MB flash, no native CAN FD (requires external transceiver + protocol stack) | Targeted at powertrain and chassis control; lacks integrated HSM and eSHE compliance | Prefer when TriCore toolchain and AUTOSAR Classic OS integration are required over Arm ecosystem compatibility |
| S32K344UAT0VLQY | Arm® Cortex®-M7 + M33 dual-core, 32-MB flash, 12-MB RAM, 10x CAN FD, but no CXPI or LIN hardware acceleration | Designed for high-end gateway and domain controller roles; higher cost and power envelope than CYT2B9 | Choose when >8 CAN FD channels, larger memory, or ISO 21434-aligned HSM are mandatory |
Compared with TC377TP-64F200N AC and S32K344UAT0VLQY, CYT2B95BACQ0AZSGST delivers optimal balance of Arm ecosystem support, integrated CXPI/LIN peripherals, ASIL-B safety features, and cost-effective 176-LQFP packaging for mid-tier automotive body electronics.
Availability
CYT2B95BACQ0AZSGST is available at Aetrix Electronics and suitable for body control modules, door module controllers, roof modules, and seat control units requiring stable component supply, automotive qualification, and long-term lifecycle support.
Supply support for CYT2B95BACQ0AZSGST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global manufacturing and R&D infrastructure.
The TRAVEO™ T2G product line was designed specifically for automotive body electronics, integrating dual-core processing, functional safety, and automotive-optimized communication peripherals (CAN FD, LIN, CXPI) in a single die.
FAQ
What is the maximum operating frequency of the Cortex-M4F core in CYT2B95BACQ0AZSGST?
The Arm® Cortex®-M4F core operates at a maximum frequency of 160 MHz, verified in the device's electrical specifications section (Section 27.11, Clock Specifications) and supported by the on-chip PLL and FLL clock sources. This frequency is achievable across the full industrial temperature range (−40°C to +125°C) under specified VDDD supply conditions.
Does CYT2B95BACQ0AZSGST support hardware-based secure boot with cryptographic signature verification?
Yes. The device implements fast secure boot using digital signature verification (RSA/ECC) via its integrated Hardware Security Module (HSM) and Enhanced Secure Hardware Extension (eSHE). Boot images are authenticated before execution, and the crypto engine supports SHA-256/512, AES-GCM, and TRNG for key derivation and integrity checks.
How many CAN FD channels are physically implemented and electrically validated on CYT2B95BACQ0AZSGST?
CYT2B95BACQ0AZSGST implements eight fully independent CAN FD channels, each with dedicated TX/RX pins and ISO 11898-1:2015 compliance. All eight channels are electrically validated per the datasheet's AC specifications (Section 27.8) and hold ISO 16845:2015 conformance certification for interoperability testing.
Is the 176-LQFP package of CYT2B95BACQ0AZSGST AEC-Q100 qualified and what grade does it meet?
Yes. The 176-LQFP variant (CYT2B95BACQ0AZSGST) is AEC-Q100 qualified for Grade 2 (−40°C to +105°C ambient) and Grade 1 (−40°C to +125°C junction) operation. Qualification documentation, including HTOL, TC, and ESD test reports, is available through Infineon's official product change notifications and qualification summary documents.
CYT2B95BACQ0AZSGST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 100-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 57x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B95BACQ0AZSGST FAQ
1.How can I place an order for CYT2B95BACQ0AZSGST through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B95BACQ0AZSGST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B95BACQ0AZSGST reliable?
The price and inventory of CYT2B95BACQ0AZSGST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B95BACQ0AZSGST is usually 5 days.
3.What payment methods are accepted for CYT2B95BACQ0AZSGST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B95BACQ0AZSGST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B95BACQ0AZSGST?
CYT2B95BACQ0AZSGST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B95BACQ0AZSGST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B95BACQ0AZSGST?
For technical support, including CYT2B95BACQ0AZSGST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B95BACQ0AZSGST requirements.
6.How does Aetrix verify that CYT2B95BACQ0AZSGST is sourced from the original manufacturer or authorized distributors?
All CYT2B95BACQ0AZSGST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B95BACQ0AZSGST meets industry standards.
7.What is the process for return or replacement of CYT2B95BACQ0AZSGST?
All CYT2B95BACQ0AZSGST units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B95BACQ0AZSGST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B95BACQ0AZSGST part is unused and in its original packaging.
Return procedure for CYT2B95BACQ0AZSGST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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