Infineon Technologies CYT2B95CACQ0AZEGST
- Part No.:
- CYT2B95CACQ0AZEGST
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
CYT2B95CACQ0AZEGST.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 100QFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,294
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Product details
Overview
CYT2B95CACQ0AZEGST from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112-KB code-flash with RWW support, hardware crypto engine (AES-128/192/256, SHA-256/512, TRNG), and ASIL-B functional safety certification. It targets body control modules requiring CAN FD (up to 8 channels), LIN (up to 12), and CXPI (up to 4) in 12 V automotive power domains.
For engineers reviewing the CYT2B95CACQ0AZEGST datasheet, CYT2B95CACQ0AZEGST pinout, CYT2B95CACQ0AZEGST application, or CYT2B95CACQ0AZEGST equivalent, this page delivers verified technical context, package-specific pin mapping, real-world use cases in automotive ECUs, and validated alternative parts for design continuity and supply resilience.
Technical Context
The CYT2B95CACQ0AZEGST implements a tightly coupled dual-CPU architecture: the M4F handles primary application processing with single-cycle multiply and FPU, while the M0+ manages peripheral offload, security services (eSHE/HSM), and secure boot via digital signature verification. Inter-processor communication is handled in hardware with dedicated mailbox and semaphore resources.
It integrates three DMA controllers (P-DMA0: 92 channels, P-DMA1: 44, M-DMA0: 4), SECDED ECC on all safety-critical memories, and a Peripheral Protection Unit (PPU) enforcing access rights per peripheral instance. Clock supervision includes IMO, ILO, ECO, WCO, PLL, and FLL - enabling robust timing across sleep/wakeup transitions and fault recovery.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, enabling real-time application + security/peripheral isolation |
| Flash Memory | 2112-KB code-flash + 128-KB work-flash; supports Read-While-Write and dual-bank firmware update for FOTA |
| SRAM | 256-KB with configurable retention granularity, allowing selective memory retention during low-power Sleep modes |
| Crypto Engine | AES-128/192/256, SHA-256/512, TRNG, RSA/ECC vector unit, and GCM mode - certified for eSHE and HSM compliance |
| Automotive Interfaces | 8 CAN FD channels (ISO 11898-1:2015, up to 8 Mbps), 12 LIN (ISO 17987), 4 CXPI (20 kbps) - all runtime-reconfigurable |
| Safety Certification | ASIL-B compliant with MPU, SMPU, PPU, SECDED ECC on SRAM/flash, BOD/LVD/OVD, and multi-counter watchdog (MCWDT) |
| Analog Peripherals | Three 12-bit SAR ADCs (67 total external channels, 1 Msps max), synchronized sampling for motor-sense applications |
Pinout & Package
CYT2B95CACQ0AZEGST is packaged in a 176-pin LQFP (24 × 24 × 1.7 mm, 0.5-mm pitch) with automotive-grade thermal and mechanical specifications. Pin assignments include dedicated VDDD/VDDA/VCCD power domains, multiple GPIO banks with enhanced drive strength, and dedicated pins for CAN FD transceivers, LIN bus, CXPI, ECO/WCO crystals, and SWD/JTAG debug interface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDD / VDDA / VCCD | Power Supply Inputs | Separate 2.7–5.5 V domains for digital core, analog, and clock circuitry - enables independent power gating and noise isolation |
| P0[0]–P11[15] | GPIO (152 total) | Configurable as GPIO_STD or GPIO_ENH; supports wakeup from Sleep/DeepSleep, event generation, and Smart I/O Boolean logic |
| CANFD0_TX / CANFD0_RX | CAN FD Channel 0 Interface | Differential pair supporting ISO 11898-1:2015; requires external transceiver; supports bit rates up to 8 Mbps |
| LIN0_TX / LIN0_RX | LIN Channel 0 Interface | Single-wire UART-compatible interface compliant with ISO 17987; supports auto-baud detection and slave node response |
| CXPI0_CLK / CXPI0_DATA | CXPI Channel 0 Interface | Single-wire bidirectional interface at 20 kbps; used for low-cost body electronics communication (e.g., door modules) |
| TCK / TMS / TDI / TDO / nTRST / SWDIO / SWCLK | Debug Interface | IEEE-1149.1 JTAG and Arm SWD compliant; supports ETM instruction/data trace and secure debug authentication |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Subsystem | Hardware-isolated M4F (160 MHz) and M0+ (100 MHz) with inter-processor mailbox and shared memory protection (SMPU) |
| Firmware Update Capability | Dual-bank flash with RWW allows seamless over-the-air (FOTA) updates without halting application execution |
| Secure Boot & Authentication | Fast secure boot using digital signature verification (RSA/ECC); supports HSM-compliant key storage and lifecycle management |
| Low-Power Operation | Five power modes (Active, Sleep, Low-power Sleep, DeepSleep, Hibernate) with configurable BOD thresholds and pin/event wakeup sources |
| Motor Control Support | 12 dedicated 16-bit motor timers + synchronized triple ADC sampling - enables field-oriented control (FOC) without CPU intervention |
Applications
| Body Control Module (BCM) | Door Control Unit (DCU) |
|---|---|
|
Use Scenario: Centralized control of lighting, windows, locks, mirrors, and seat position in passenger vehicles. IC Role / Device Role / Timing Role: Primary MCU managing CAN FD backbone communication, LIN subnets for door modules, and real-time PWM for LED dimming. Use Value: Dual-core architecture isolates safety-critical lock actuation (M0+) from infotainment-linked lighting (M4F), meeting ASIL-B requirements. |
Use Scenario: Intelligent door module integrating window lift, mirror fold, and proximity sensing. IC Role / Device Role / Timing Role: Local controller interfacing with LIN master (BCM) and driving brushed/BLDC motors via TCPWM with dead-time insertion. Use Value: Integrated 12-bit ADCs and synchronized sampling enable precise current sensing for motor stall detection and soft-start control. |
| Roof Control Module (RCM) | Smart Junction Box (SJB) |
|
Use Scenario: Sunroof, panoramic roof, and ambient lighting control with tilt/slide position feedback. IC Role / Device Role / Timing Role: Real-time position tracking via quadrature encoder inputs and PWM-driven actuator control with fault-safe shutdown. Use Value: 75× 16-bit TCPWM blocks support simultaneous multi-axis motion profiles and CRC-protected command validation over CXPI. |
Use Scenario: Power distribution and load monitoring across chassis domains (lighting, HVAC, wipers). IC Role / Device Role / Timing Role: High-integration MCU performing load switching, current sensing (via SAR ADC), and CAN FD diagnostics reporting. Use Value: Hardware crypto engine enables secure firmware updates and authenticated communication with gateway ECUs, preventing unauthorized reprogramming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TC377TP-64F200N-DC | TriCore™ AURIX™ TC3xx family; 200-MHz TriCore CPU + 100-MHz ARM M0+; no integrated CXPI; higher CAN FD count (10 channels) | Targeted at powertrain and ADAS; lacks native CXPI support but offers stronger ASIL-D capability and larger safety memory | Select when ASIL-D compliance or higher CAN FD channel density is required; requires external CXPI transceiver if needed |
| S32K344UAT0VLQ | NXP S32K3 series; 320-MHz Arm® Cortex®-M7 + M0+; includes Ethernet AVB, no CXPI; supports ISO 26262 ASIL-D | Designed for zonal gateways and domain controllers; emphasizes high-speed networking over low-cost body protocols | Prefer for next-gen vehicle architectures needing Ethernet integration; not drop-in due to different peripheral set and pinout |
Compared with TC377TP-64F200N-DC and S32K344UAT0VLQ, CYT2B95CACQ0AZEGST uniquely balances ASIL-B compliance, CXPI integration, and cost-optimized LQFP packaging - making it optimal for mid-tier body electronics where protocol diversity and footprint matter more than ASIL-D or Ethernet.
Availability
CYT2B95CACQ0AZEGST is available at Aetrix Electronics and suitable for body control modules, door control units, roof control modules, and smart junction boxes requiring stable component supply under AEC-Q100 Grade 2 qualification and long-term automotive lifecycle support.
Supply support for CYT2B95CACQ0AZEGST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global manufacturing and automotive qualification expertise.
CYT2B9 belongs to the TRAVEO™ T2G family - designed specifically for automotive body electronics requiring dual-core processing, integrated CAN FD/LIN/CXPI, and hardware-enforced security for ECU-level firmware integrity and safe operation.
FAQ
Does CYT2B95CACQ0AZEGST support over-the-air (FOTA) firmware updates?
Yes. It features dual-bank flash architecture with Read-While-Write capability, enabling background firmware updates without interrupting application execution. The bootloader validates new images using RSA/ECC digital signatures before activation, ensuring authenticity and integrity per UNECE R155 requirements.
What is the maximum operating temperature range for CYT2B95CACQ0AZEGST?
This part is qualified to AEC-Q100 Grade 2, supporting operation from –40 °C to +105 °C ambient temperature. Its internal regulators, thermal monitoring diode, and BOD thresholds are characterized across this full range, with derating applied above 105 °C junction temperature per datasheet Section 27.2.
Can CYT2B95CACQ0AZEGST directly drive a CAN FD transceiver without level-shifting?
Yes. Its CAN FD I/O pins are 5-V tolerant and comply with ISO 11898-1:2015 physical layer signaling levels. They interface directly with standard high-speed CAN FD transceivers (e.g., TJA1044, IFX1050) without external level shifters, provided proper termination and layout guidelines are followed.
Is the crypto engine in CYT2B95CACQ0AZEGST certified to any security standards?
The hardware crypto engine supports eSHE and HSM functionality aligned with ISO/SAE 21434 and EVITA Medium profiles. While not individually Common Criteria certified, its implementation meets Infineon's internal HSM security requirements for secure boot, key provisioning, and cryptographic acceleration in automotive ECUs.
CYT2B95CACQ0AZEGST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 100-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 57x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B95CACQ0AZEGST FAQ
1.How can I place an order for CYT2B95CACQ0AZEGST through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B95CACQ0AZEGST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B95CACQ0AZEGST reliable?
The price and inventory of CYT2B95CACQ0AZEGST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B95CACQ0AZEGST is usually 5 days.
3.What payment methods are accepted for CYT2B95CACQ0AZEGST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B95CACQ0AZEGST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B95CACQ0AZEGST?
CYT2B95CACQ0AZEGST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B95CACQ0AZEGST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B95CACQ0AZEGST?
For technical support, including CYT2B95CACQ0AZEGST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B95CACQ0AZEGST requirements.
6.How does Aetrix verify that CYT2B95CACQ0AZEGST is sourced from the original manufacturer or authorized distributors?
All CYT2B95CACQ0AZEGST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B95CACQ0AZEGST meets industry standards.
7.What is the process for return or replacement of CYT2B95CACQ0AZEGST?
All CYT2B95CACQ0AZEGST units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B95CACQ0AZEGST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B95CACQ0AZEGST part is unused and in its original packaging.
Return procedure for CYT2B95CACQ0AZEGST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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