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Infineon Technologies CYT2B95CACQ0AZSGS

Name: CYT2B95CACQ0AZSGS
Brand: Infineon Technologies
SKU: CYT2B95CACQ0AZSGS
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: CYT2B95CACQ0AZSGS

Manufacturer:: Infineon Technologies

Category:: Microcontrollers

Package:: 100-LQFP

Datasheet:: CYT2B95CACQ0AZSGS.pdf

Description:: IC MCU 32BT 2.0625MB FLSH 100QFP

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Product details

Overview

CYT2B95CACQ0AZSGS from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112 KB code-flash with RWW support, 256 KB SRAM, and integrated CAN FD (up to 8 channels), LIN (up to 12 channels), and CXPI (up to 4 channels). It targets body control modules requiring ASIL-B functional safety, secure boot, and hardware crypto acceleration including AES-128/192/256, SHA-256/512, and ECC.

For engineers reviewing the CYT2B95CACQ0AZSGS datasheet, CYT2B95CACQ0AZSGS pinout, CYT2B95CACQ0AZSGS application, or CYT2B95CACQ0AZSGS equivalent, this part supports fine-grained power management across Hibernate/Sleep/DeepSleep modes, synchronized multi-ADC sampling for motor sensing, and hardware inter-processor communication-critical for automotive ECU consolidation and OTA firmware updates.

Technical Context

The CYT2B95CACQ0AZSGS implements a tightly coupled dual-CPU architecture where the M4F handles real-time application processing while the M0+ manages peripheral offload, security services (eSHE/HSM), and safety-critical tasks. Its memory subsystem includes SECDED ECC on all safety-critical SRAM and flash, MPU/SMPU enforcement, and PPU-protected peripherals.

It integrates three DMA controllers (P-DMA0 with 92 channels, P-DMA1 with 44, M-DMA0 with 4), seven RTC-triggered EVTGEN timers for DeepSleep wakeup, and five Smart I/O blocks enabling Boolean logic on GPIO_STD signals-enabling deterministic low-latency I/O response without CPU intervention.

Key Specifications

Parameter	Value and Actual Design Meaning
CPU Cores	Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, with hardware IPC and separate MPUs
Memory	2112 KB code-flash (RWW, dual-bank FOTA), 128 KB work-flash, 256 KB SRAM with configurable retention
Crypto Engine	AES-128/192/256, SHA-256/512, ECC, RSA, TRNG/PRNG, GCM mode-all hardware-accelerated
Automotive Interfaces	Up to 8 CAN FD channels (ISO 11898-1:2015 compliant), 12 LIN (ISO 17987), 4 CXPI (20 kbps)
Analog Peripherals	Three SAR ADCs (12-bit, 1 Msps each), 67 total external channels, synchronized sampling across all ADCs
Power Modes	ASIL-B compliant: Hibernate, DeepSleep, Low-power Sleep, Sleep, Active-with BOD at 2.7 V/3.0 V (VDDD/VDDA) and 1.1 V (VCCD)
Package	176-LQFP, 24 × 24 × 1.7 mm, 0.5-mm pitch, RoHS-compliant, automotive-grade (–40°C to +125°C)

Pinout & Package

CYT2B95CACQ0AZSGS is housed in a 176-pin LQFP package (24 × 24 × 1.7 mm, 0.5-mm pitch) with dedicated power, ground, analog reference, clock, debug (SWD/JTAG), and high-speed I/O banks. Pin functions include VDDD/VDDA/VCCD supplies, POR/BOD reset inputs, IMO/ILO/ECO/WCO clock sources, CAN FD TX/RX differential pairs, LIN transceiver pins, CXPI data lines, and GPIO_STD/GPIO_ENH with Smart I/O capability.

Pin/Terminal	Circuit Role	Design Meaning
VDDD, VDDA, VCCD	Core, Analog, and Digital Regulator Inputs	Separate 2.7–5.5 V supply domains enable independent noise isolation and power gating per subsystem
TCK, TMS, TDI, TDO, nTRST, SWDIO, SWCLK	JTAG/SWD Debug Interface	IEEE-1149.1-compliant boundary scan and Arm® SWD for production programming and runtime debugging
CANFD0_TX, CANFD0_RX	Differential CAN FD Transceiver Interface	Direct connection to external CAN FD transceiver; supports up to 8 Mbps data rate per channel
LIN0_TX, LIN0_RX	Single-Wire LIN Bus Interface	Compliant with ISO 17987; supports up to 12 independent LIN channels with automatic baud rate detection
CXPI0_DATA	CXPI Physical Layer Data Line	Single-wire bus interface supporting up to 4 CXPI channels at 20 kbps for low-cost vehicle networking
ADC0_IN0–ADC0_IN23	SAR ADC Channel Inputs	24 logical channels mapped to 25 physical pins; supports external multiplexer addressing and sequenced autonomous conversion

Key Features

Feature	Design Value
Dual-CPU Hardware IPC	Zero-latency mailbox and semaphore registers between M4F and M0+ enable deterministic task partitioning without software polling
RWW Flash Architecture	Simultaneous execution from one flash bank while programming another-enables safe, atomic FOTA updates without system halt
Multi-ADC Synchronization	Hardware-triggered simultaneous sampling across all three SAR ADCs supports precise motor phase current and voltage measurement
Smart I/O Logic Blocks	Five programmable logic units perform Boolean operations (AND/OR/XOR) on GPIO_STD signals-reducing CPU load for sensor fusion or fault monitoring
ASIL-B Safety Mechanisms	SECDED ECC on SRAM/flash, SMPU for shared memory access control, PPU for peripheral protection, and dual watchdogs (WDT/MCWDT)

Applications

Body Control Module (BCM)

Door Module Controller

Use Scenario: Centralized control of lighting, window lift, mirror adjustment, and door lock actuation in modern vehicles.

IC Role / Device Role / Timing Role: Primary MCU managing LIN/CAN FD communication with sub-nodes, executing safety-critical diagnostics, and coordinating OTA updates.

Use Value: Dual-core separation isolates LIN protocol stack (M0+) from application logic (M4F), ensuring deterministic response under bus load while maintaining ASIL-B compliance.

Use Scenario: Local intelligence in vehicle doors for anti-pinch detection, position sensing, and proximity-based unlock.

IC Role / Device Role / Timing Role: Real-time motor control via TCPWM blocks and synchronized ADC sampling for current/voltage feedback loops.

Use Value: 75× 16-bit TCPWM blocks with dead-time insertion and 12× motor-control counters enable precise BLDC commutation without external gate drivers.

Roof Module Controller

Seat Control Unit

Use Scenario: Sunroof, panoramic roof, and ambient lighting control with gesture and proximity sensing.

IC Role / Device Role / Timing Role: Secure hub aggregating CXPI-sensed switch inputs and driving RGB LED strings via PWM.

Use Value: Four CXPI channels reduce wiring harness weight vs. LIN; Smart I/O blocks preprocess multi-switch inputs before M0+ dispatches events to M4F.

Use Scenario: Power seat positioning with memory presets, heating, ventilation, and posture sensing.

IC Role / Device Role / Timing Role: Integrated motor driver interface, thermal monitoring via calibrated diode, and secure parameter storage in encrypted flash.

Use Value: On-chip TRNG and AES-GCM enable encrypted seat profile storage; SAR ADCs monitor heater element resistance and thermistor voltage simultaneously.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
S32K344LHT0VLQY	NXP S32K3 series: 300-MHz Arm® Cortex®-M7 + M7 dual-core; no integrated CXPI; higher CAN FD count (12); different crypto IP (CAAM)	Targets gateway and domain controller roles; lacks native CXPI support required for cost-sensitive body nodes	Select when higher compute throughput and CAN FD bandwidth are prioritized over CXPI integration and lower BOM cost
TC377TP-64F200N	Infineon AURIX™ TC3xx: Tri-core (2× TriCore + 1× Cortex®-M7); no LIN/CXPI; focused on powertrain/safety-critical ADAS	Designed for ASIL-D systems; lacks LIN/CXPI peripherals essential for body electronics communication	Choose only for powertrain or chassis control where ASIL-D certification and deterministic TriCore timing outweigh body-network interface needs

Compared with S32K344LHT0VLQY and TC377TP-64F200N, CYT2B95CACQ0AZSGS uniquely balances ASIL-B compliance, native CXPI/LIN/CAN FD coexistence, and dual-core workload partitioning-making it optimal for consolidated body ECUs where interface diversity and OTA security are non-negotiable.

Availability

CYT2B95CACQ0AZSGS is available at Aetrix Electronics and suitable for automotive body control modules, door/roof/seat control units, and centralized lighting systems requiring stable component supply, long lifecycle support, and automotive-grade qualification (AEC-Q100 Grade 1).

Supply support for CYT2B95CACQ0AZSGS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global R&D and manufacturing infrastructure.

CYT2B95CACQ0AZSGS belongs to the TRAVEO™ T2G family-designed specifically for automotive body electronics consolidation, emphasizing interface flexibility (CAN FD/LIN/CXPI), functional safety (ASIL-B), and secure over-the-air update capability.

FAQ

What is the maximum operating temperature range for CYT2B95CACQ0AZSGS?

CYT2B95CACQ0AZSGS is qualified for automotive Grade 1 operation, with a junction temperature range of –40°C to +125°C. This rating is validated per AEC-Q100 and applies across all supported power modes, including Active and Hibernate, with thermal derating applied per datasheet Section 27.2.

Does CYT2B95CACQ0AZSGS support hardware-based secure boot with signature verification?

Yes. The device implements fast secure boot using digital signature verification (ECDSA or RSA) enforced by the hardware crypto engine. Boot ROM validates the signature of the first-stage bootloader before execution, with keys stored in eFuses or protected flash. This process is mandatory and cannot be disabled.

How many CAN FD channels are physically implemented on CYT2B95CACQ0AZSGS in the 176-LQFP package?

The CYT2B95CACQ0AZSGS in 176-LQFP supports all eight CAN FD channels specified in the family datasheet. Pin assignments for CANFD0–CANFD7 are fully allocated in this package variant, with dedicated differential pairs routed to separate I/O banks to minimize crosstalk and ensure signal integrity at 8 Mbps.

Is the 256 KB SRAM banked or unified, and does it support retention in DeepSleep mode?

The 256 KB SRAM is unified but supports configurable retention granularity: individual 4-KB blocks can be selectively retained during DeepSleep mode. Retention is controlled via the PMU register map, and retained blocks maintain data integrity without refresh-enabling low-power context preservation for wake-up handlers and critical state variables.

CYT2B95CACQ0AZSGS Specifications

Product attributes: Attribute value

Manufacturer:: Infineon Technologies

Package/Case:: 100-LQFP

Series:: Traveo™ T2G

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Core Processor:: ARM® Cortex®-M0+, ARM® Cortex®-M4F

Core Size:: 32-Bit Dual-Core

Speed:: 100MHz, 160MHz

Connectivity:: CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART

Peripherals:: Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT

Number of I/O:: 78

Program Memory Size:: 2.0625MB (2.0625M x 8)

Program Memory Type:: FLASH

EEPROM Size:: 128K x 8

RAM Size:: 256K x 8

Voltage - Supply (Vcc/Vdd):: 2.7V ~ 5.5V

Data Converters:: A/D 57x12b SAR

Oscillator Type:: External, Internal

Operating Temperature:: -40°C ~ 105°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:

CYT2B95CACQ0AZSGS FAQ

1.How can I place an order for CYT2B95CACQ0AZSGS through Aetrix?

Please submit a Request for Quotation (RFQ) for CYT2B95CACQ0AZSGS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for CYT2B95CACQ0AZSGS reliable?

The price and inventory of CYT2B95CACQ0AZSGS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B95CACQ0AZSGS is usually 5 days.

3.What payment methods are accepted for CYT2B95CACQ0AZSGS?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B95CACQ0AZSGS transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for CYT2B95CACQ0AZSGS?

CYT2B95CACQ0AZSGS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your CYT2B95CACQ0AZSGS order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for CYT2B95CACQ0AZSGS?

For technical support, including CYT2B95CACQ0AZSGS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B95CACQ0AZSGS requirements.

6.How does Aetrix verify that CYT2B95CACQ0AZSGS is sourced from the original manufacturer or authorized distributors?

All CYT2B95CACQ0AZSGS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B95CACQ0AZSGS meets industry standards.

7.What is the process for return or replacement of CYT2B95CACQ0AZSGS?

All CYT2B95CACQ0AZSGS units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B95CACQ0AZSGS, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The CYT2B95CACQ0AZSGS part is unused and in its original packaging.

Return procedure for CYT2B95CACQ0AZSGS:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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