Infineon Technologies CYT2B98BACQ0AZSGS
- Part No.:
- CYT2B98BACQ0AZSGS
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
CYT2B98BACQ0AZSGS.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 176QFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
CYT2B98BACQ0AZSGS from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112-KB code-flash with RWW support, 256-KB SRAM, and integrated CAN FD (up to 8 channels), LIN (up to 12 channels), and CXPI (up to 4 channels). It targets body control modules requiring ASIL-B functional safety, secure boot, and hardware crypto acceleration including AES-128/192/256, SHA-256/512, and ECC.
For engineers reviewing the CYT2B98BACQ0AZSGS datasheet, CYT2B98BACQ0AZSGS pinout, CYT2B98BACQ0AZSGS application, or CYT2B98BACQ0AZSGS equivalent, this part delivers deterministic real-time control, hardware-enforced memory protection (MPU/SMPU), SECDED ECC on flash/SRAM, and low-power DeepSleep/Hibernate modes with multi-pin wakeup-critical for automotive ECU firmware update, sensor fusion, and secure gateway design.
Technical Context
The CYT2B98BACQ0AZSGS implements a tightly coupled dual-CPU architecture: the M4F handles primary application tasks with FPU and MPU, while the M0+ offloads peripheral management, security services (eSHE/HSM), and secure boot verification. Inter-processor communication occurs via dedicated hardware mailboxes and shared memory with SMPU enforcement.
Its peripheral set includes eight CAN FD controllers compliant with ISO 11898-1:2015 and Bosch CAN FD v1.0, twelve LIN controllers meeting ISO 17987, and four CXPI interfaces operating at 20 kbps. Clocking is managed by IMO, ILO, ECO, WCO, PLL, and FLL sources, with configurable BOD thresholds (2.7 V / 3.0 V on VDDD/VDDA, 1.1 V on VCCD).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+ |
| Flash Memory | 2112-KB code-flash + 128-KB work-flash; supports Read-While-Write and dual-bank FOTA updates |
| SRAM | 256-KB with selectable retention granularity per memory block |
| CAN FD Channels | 8 independent channels; up to 8 Mbps data rate; ISO 11898-1:2015 and Bosch CAN FD v1.0 compliant |
| LIN Channels | 12 runtime-configurable channels; fully compliant with ISO 17987 |
| Crypto Engine | Hardware-accelerated AES-128/192/256, SHA-256/512, ECC, RSA, TRNG, and GCM mode |
| Functional Safety | ASIL-B compliant with MPU, SMPU, PPU, SECDED ECC on flash/SRAM, and multi-level watchdogs (WDT/MCWDT) |
Pinout & Package
CYT2B98BACQ0AZSGS is packaged in a 176-pin LQFP (24 × 24 × 1.7 mm, 0.5-mm pitch) with dedicated power, ground, analog, high-speed digital, and functional I/O banks. Pin functions include VDDD/VDDA/VCCD supplies, SWD/JTAG debug, CAN FD/LIN/CXPI transceiver interfaces, GPIO_STD/GPIO_ENH, ADC inputs, and wakeup-capable pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDD, VDDA, VCCD | Power supply rails | VDDD/VDDA = 2.7–5.5 V core/analog supply; VCCD = 1.1 V internal core regulator output |
| P0[0]–P0[7], P1[0]–P1[7], etc. | GPIO_STD / GPIO_ENH | 152 total programmable I/Os; GPIO_ENH supports enhanced slew rate, drive strength, and analog mux routing |
| CANFD0_TX/RX – CANFD7_TX/RX | CAN FD transceiver interface | Dedicated differential pairs per channel; each supports ISO 11898-1:2015 physical layer compliance |
| LIN0–LIN11 | LIN bus interface | 12 independent LIN PHY outputs; each supports ISO 17987 slave/master operation and auto-baud detection |
| CXPI0–CXPI3 | CXPI bus interface | 4 single-wire serial interfaces; 20 kbps data rate; supports wake-up and diagnostics per ISO 14230 |
| TCK, TMS, TDO, TDI, nTRST, SWDIO, SWCLK | Debug interface | Full IEEE-1149.1 JTAG and Arm® SWD support; enables ETM instruction/data trace and secure debug authentication |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU subsystem with hardware IPC | Enables real-time separation of safety-critical (M0+) and application (M4F) workloads without software arbitration overhead |
| Read-While-Write flash architecture | Allows concurrent firmware execution and over-the-air (FOTA) update of code/work-flash without system stall or external memory |
| Hardware Security Module (HSM) | Provides tamper-resistant key storage, secure boot with digital signature verification, and cryptographic acceleration for OTA firmware validation |
| ASIL-B certified safety mechanisms | Includes SECDED ECC on all safety-critical memories, Peripheral Protection Unit (PPU), and dual watchdogs (WDT + MCWDT) |
| Configurable low-power modes | Supports Hibernate (2-pin wakeup), DeepSleep (EVTGEN-triggered), and Sleep (152-GPIO wakeup) with granular retention control |
Applications
| Body Control Module (BCM) | Automotive Gateway |
|---|---|
|
Use Scenario: Centralized control of door locks, lighting, wipers, and HVAC in modern vehicle platforms. IC Role / Device Role / Timing Role: Primary MCU executing real-time control logic, managing LIN slaves (e.g., mirror controls), and coordinating CAN FD messaging between domains. Use Value: Dual-core isolation ensures safety-critical lock actuation runs independently on M0+, while M4F handles UI responsiveness and diagnostics-meeting ASIL-B requirements without software partitioning complexity. |
Use Scenario: Aggregation and translation of messages across CAN FD, LIN, and CXPI networks in zonal architectures. IC Role / Device Role / Timing Role: Protocol bridge and firewall enforcing message filtering, routing, and secure firmware updates between domains. Use Value: Eight CAN FD channels and twelve LIN ports enable simultaneous domain bridging; hardware crypto engine validates signed OTA updates before execution-preventing unauthorized firmware injection. |
| Electric Power Steering (EPS) Support MCU | Secure Telematics Control Unit (TCU) |
|
Use Scenario: Sensor preprocessing, motor phase current sampling, and fault monitoring for EPS assist systems. IC Role / Device Role / Timing Role: Real-time ADC acquisition (synchronized 3× SAR converters), PWM generation with dead-time insertion, and CAN FD feedback to main EPS ECU. Use Value: 12-bit, 1-Msps SAR ADCs with sequencer-driven autonomous scanning reduce CPU load; TCPWM blocks deliver precise motor control timing with <100 ns dead-time resolution. |
Use Scenario: Cellular modem coordination, GNSS data handling, and secure V2X message signing in connected vehicles. IC Role / Device Role / Timing Role: Secure co-processor managing TLS handshake offload, certificate validation, and encrypted log storage using HSM-backed keys. Use Value: Hardware-accelerated AES-GCM and SHA-512 enable low-latency encryption of telematics payloads; TRNG feeds entropy into TLS PRF-meeting UNECE R155 cybersecurity management system (CSMS) requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP S32K344 | Single-core Arm® Cortex®-M7 (320 MHz); no M0+ companion core; includes HSE security module but lacks native CXPI support | Stronger compute throughput for motor control algorithms; limited to CAN FD + LIN only-no CXPI for legacy body networks | Select when higher M7 performance is required and CXPI is not needed; verify LIN/CAN FD channel count matches system topology |
| Renesas RH850/U2A | 32-bit RH850 core (240 MHz); proprietary ISA; integrated CAN FD (6 ch), LIN (10 ch), but no hardware crypto accelerator or RWW flash | Proven in Japanese OEM BCMs; requires external secure element for OTA signature verification and lacks FOTA-ready flash architecture | Prefer where existing RH850 toolchain and ecosystem integration outweigh need for integrated HSM and dual-bank flash |
Compared with S32K344 and RH850/U2A, CYT2B98BACQ0AZSGS uniquely combines dual-core deterministic partitioning, native CXPI support, RWW flash for seamless FOTA, and full HSM-based secure boot-making it optimal for next-gen zonal gateways requiring protocol diversity and embedded trust anchors.
Availability
CYT2B98BACQ0AZSGS is available at Aetrix Electronics and suitable for automotive body control modules, zonal gateways, electric power steering support units, and secure telematics control units requiring stable component supply, long lifecycle commitment, and ASIL-B certification.
Supply support for CYT2B98BACQ0AZSGS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global manufacturing and R&D centers across Europe, Asia, and the Americas.
CYT2B98BACQ0AZSGS belongs to the TRAVEO™ T2G family, designed specifically for automotive body electronics and domain controllers requiring functional safety, secure firmware execution, and multi-protocol connectivity (CAN FD/LIN/CXPI) in harsh environments.
FAQ
What is the maximum operating frequency of each CPU core in CYT2B98BACQ0AZSGS?
The Arm® Cortex®-M4F core operates at up to 160 MHz, delivering 200 DMIPS performance with single-cycle multiply and hardware FPU support. The Arm® Cortex®-M0+ core runs at up to 100 MHz, optimized for deterministic peripheral and security processing with its own MPU and dedicated DMA channels.
Does CYT2B98BACQ0AZSGS support Over-The-Air (OTA) firmware updates?
Yes. It supports robust OTA updates via dual-bank flash architecture (code-flash + work-flash), Read-While-Write capability, and hardware-accelerated secure boot using digital signatures verified by the integrated HSM. This enables atomic firmware swaps without system interruption or external memory dependency.
How many CAN FD channels does CYT2B98BACQ0AZSGS provide, and what standards do they meet?
CYT2B98BACQ0AZSGS integrates eight independent CAN FD controllers. Each complies with ISO 11898-1:2015 and satisfies all mandatory requirements of the Bosch CAN FD Specification V1.0, supporting data rates up to 8 Mbps depending on physical layer implementation and transceiver selection.
Is CYT2B98BACQ0AZSGS qualified for automotive temperature grade and reliability standards?
Yes. It is AEC-Q100 Grade 2 qualified (−40 °C to +105 °C ambient), manufactured on Infineon's 40-nm automotive process, and features built-in reliability mechanisms including SECDED ECC on flash/SRAM, brown-out detection with dual thresholds, and hardware watchdog supervision across all power modes.
CYT2B98BACQ0AZSGS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 176-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 152
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 82x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B98BACQ0AZSGS FAQ
1.How can I place an order for CYT2B98BACQ0AZSGS through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B98BACQ0AZSGS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B98BACQ0AZSGS reliable?
The price and inventory of CYT2B98BACQ0AZSGS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B98BACQ0AZSGS is usually 5 days.
3.What payment methods are accepted for CYT2B98BACQ0AZSGS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B98BACQ0AZSGS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B98BACQ0AZSGS?
CYT2B98BACQ0AZSGS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B98BACQ0AZSGS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B98BACQ0AZSGS?
For technical support, including CYT2B98BACQ0AZSGS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B98BACQ0AZSGS requirements.
6.How does Aetrix verify that CYT2B98BACQ0AZSGS is sourced from the original manufacturer or authorized distributors?
All CYT2B98BACQ0AZSGS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B98BACQ0AZSGS meets industry standards.
7.What is the process for return or replacement of CYT2B98BACQ0AZSGS?
All CYT2B98BACQ0AZSGS units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B98BACQ0AZSGS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B98BACQ0AZSGS part is unused and in its original packaging.
Return procedure for CYT2B98BACQ0AZSGS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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