Infineon Technologies MB90F352ESPMC1-GS-SPE2

Overview

MB90F352ESPMC1-GS-SPE2 from Infineon Technologies (formerly Cypress) is a 16-bit F2MC-16LX microcontroller with integrated FULL-CAN 2.0A/B interface, 128 KB dual-operation Flash memory, and 15-channel 8/10-bit ADC. It operates at up to 24 MHz (42 ns instruction cycle), supports LIN-UART (2 ch), I²C (400 kbps), and runs on 3.5–5.5 V supply. Designed for automotive body control modules requiring CAN-based distributed sensing and actuation.

For engineers reviewing the MB90F352ESPMC1-GS-SPE2 datasheet, MB90F352ESPMC1-GS-SPE2 pinout, MB90F352ESPMC1-GS-SPE2 application, or MB90F352ESPMC1-GS-SPE2 equivalent, key selection criteria include CAN message buffer count (16), dual-bank Flash security, sub-clock independence (no X0A/X1A pins), and industrial-grade temperature range (−40°C to +125°C).

Technical Context

The MB90F352ESPMC1-GS-SPE2 implements a dedicated FULL-CAN controller compliant with ISO 11898-1:2003, supporting bit rates up to 1 Mbps and automatic retransmission on error. Its 16 prioritized message buffers enable flexible acceptance filtering via full-bit compare, full-bit mask, or dual partial masks - eliminating need for software-based ID filtering.

It integrates a PLL clock multiplier (×1 to ×6 on 4 MHz crystal), delivering 24 MHz system clock with 42 ns minimum instruction execution time. The device lacks sub-clock pins (X0A/X1A), confirming S-suffix designation, and uses internal CR oscillation for low-power watch mode - distinct from non-S variants with external sub-clock support.

Key Specifications

Pinout & Package

LQFP-64 package with 10 mm × 10 mm footprint, 0.5 mm pitch, and exposed thermal pad (EP). Pinout validated per Cypress Document 002-04493 Rev. *A, Page 13–14.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit automotive microcontroller applications.

Compared with MB90F352TEPMC1-GS-SPE2 and MB90F357ESPMC1-GS-SPE2, the MB90F352ESPMC1-GS-SPE2 provides optimal cost/performance balance for non-safety-critical CAN nodes where voltage supervision and clock monitoring are handled externally.

Availability

MB90F352ESPMC1-GS-SPE2 is available at Aetrix Electronics and suitable for automotive body electronics, industrial CAN gateways, and embedded telematics systems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MB90F352ESPMC1-GS-SPE2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies acquired Cypress Semiconductor in 2020 and maintains its automotive microcontroller portfolio with full technical and supply chain continuity.

The MB90350E Series targets automotive and industrial real-time control applications, emphasizing CAN-native communication, robust Flash security, and extended temperature operation without external supervisory ICs.

FAQ

Does MB90F352ESPMC1-GS-SPE2 support CAN FD?

No. This device implements only classical CAN 2.0A/B protocol with maximum 1 Mbps bit rate and 8-byte payload per frame. It lacks CAN FD features such as variable bit rate switching, extended data length (up to 64 bytes), and CRC enhancements. For CAN FD, consider Infineon's newer AURIX™ TC3xx family.

What is the purpose of the "S" suffix in MB90F352ESPMC1-GS-SPE2?

The "S" suffix indicates absence of sub-clock pins (X0A/X1A), meaning the device relies solely on internal CR oscillation for low-power watch mode - no external 32.768 kHz crystal is supported. This simplifies board layout and reduces BOM count versus non-S variants that require external sub-clock components.

Can the 128 KB Flash be programmed in-system via CAN or LIN?

Yes. The dual-operation Flash architecture allows background programming: while application code executes from one bank, firmware updates can be written to the other bank via LIN-UART or CAN using Cypress-provided bootloader routines. No external programmer is needed after initial flash provisioning.

Is the 15-channel ADC shared across all pins or limited to specific port groups?

All 15 ADC channels map to dedicated analog input pins (AD0–AD14) located on Port 3 and Port 4 - not multiplexed with general-purpose I/O. Each channel connects directly to internal sample-and-hold circuitry; no port configuration is required to enable analog input functionality.