Infineon Technologies MB90F352PFM-G-JNE1

Overview

MB90F352PFM-G-JNE1 from Fujitsu is a 16-bit F2MC-16LX microcontroller with integrated FULL-CAN interface (V2.0 Part A/B), 128 KB Flash ROM, 4 KB RAM, and 15-channel 8/10-bit ADC. It operates at up to 24 MHz (PLL ×6 from 4 MHz crystal), delivers 42 ns instruction execution time, and supports automotive-grade operation from −40 °C to +105 °C in LQFP-64 package. Used in body control modules requiring CAN-based sensor/actuator communication and real-time I/O timing.

For engineers reviewing the MB90F352PFM-G-JNE1 datasheet, MB90F352PFM-G-JNE1 pinout, MB90F352PFM-G-JNE1 application, or MB90F352PFM-G-JNE1 equivalent, key selection criteria include CAN message buffer flexibility (16 mailboxes + FIFO mixing), dual-bank flash security (MB90F352x only), sub-clock independence for watchdog timing, and 16-bit freerun timer pairing with ICU/OCU for precise PWM capture/generation.

Technical Context

The MB90F352PFM-G-JNE1 implements the F2MC-16LX CPU core with 24-bit internal addressing and 16 MB memory space, supporting bit/byte/word/long-word data types and 23 addressing modes. Its PLL multiplies external 4 MHz clock by 1–6×, enabling 4–24 MHz machine clock and 42 ns min instruction cycle.

Peripheral integration includes two 16-bit freerun timers (FRT0/FRT1), six 16-bit input capture channels (ICU), four 16-bit output compare channels (OCU), two UARTs with LIN/SCI support, one I²C interface (400 kbps), and a 15-channel ADC with selectable 8-/10-bit resolution and 3 µs conversion time at 24 MHz.

Key Specifications

Pinout & Package

MB90F352PFM-G-JNE1 is housed in a 64-pin LQFP package (FPT-64P-M24, 10 mm × 10 mm, 0.50 mm pitch) with exposed thermal pad. Pin functions are validated per DS07-13737-4E Rev.4.0, including dedicated CANH/CANL, X0A/X1A sub-clock inputs, FRCK0/FRCK1 freerun timer clocks, and ICU/OCU signal mapping.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit automotive microcontroller applications.

Compared with RL78/F13 and S12XEP100, MB90F352PFM-G-JNE1 uniquely balances 16-bit deterministic timing, dual-bank Flash security, and sub-clock autonomy-enabling robust, self-contained operation in space-constrained automotive nodes where CAN latency and firmware integrity are critical.

Availability

MB90F352PFM-G-JNE1 is available at Aetrix Electronics and suitable for body control modules, electronic power steering units, engine cooling fan controllers, and industrial CAN gateways requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MB90F352PFM-G-JNE1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Fujitsu Semiconductor (now part of Socionext Inc.) designed high-reliability microcontrollers for automotive and industrial markets, emphasizing functional safety, EMI resilience, and long-term supply stability.

The MB90350 Series targets automotive body electronics and chassis systems, integrating FULL-CAN, precision analog peripherals, and low-power modes to meet AEC-Q100 Grade 2 requirements without external support ICs.

FAQ

Does MB90F352PFM-G-JNE1 support CAN FD?

No. MB90F352PFM-G-JNE1 implements FULL-CAN compliant with ISO 11898-1 V2.0 Part A and Part B only, supporting data rates up to 1 Mbps with standard/extended identifiers. It does not support CAN FD's variable bit rate, larger payload, or CRC enhancements. For CAN FD, consider Socionext's newer MB96F series or Renesas RH850.

What is the purpose of the X0A/X1A pins on MB90F352PFM-G-JNE1?

X0A and X1A are dedicated sub-clock oscillator inputs supporting external 100 kHz crystals for independent low-power timing. They enable watch mode operation (sub-clock + watch timer only) and clock monitor functionality. Internal CR oscillation (100 kHz typical) can substitute for external crystal when X0A/X1A are unconnected.

How many simultaneous CAN message buffers does MB90F352PFM-G-JNE1 support?

MB90F352PFM-G-JNE1 provides 16 prioritized message buffers that support flexible configuration: full-bit compare, full-bit mask, or two partial bit masks. Buffers can be assigned as mailboxes (dedicated ID filtering) or FIFOs (sequential storage), and both types may coexist within the same CAN controller instance.

Is the Flash memory on MB90F352PFM-G-JNE1 capable of concurrent read/erase operations?

Yes. As an "A-suffix" device (MB90F352A), MB90F352PFM-G-JNE1 features dual-operation Flash memory: erase/write in one bank (Upper or Lower) while reading from the other. This enables live firmware updates and background programming without halting application execution.