Infineon Technologies MB90F543GSPF-GS

Overview

MB90F543GSPF-GS from Cypress Semiconductor is a 16-bit F2MC-16LX microcontroller with dual FULL-CAN interfaces (CAN 2.0A/B), 128 KB Flash ROM, 6 KB RAM, and 100-pin LQFP package. It operates at up to 16 MHz system clock (via on-chip PLL ×4), delivers 62.5 ns minimum instruction execution time, and targets automotive body control modules requiring robust CAN communication, analog sensing, and real-time I/O timing.

For engineers reviewing the MB90F543GSPF-GS datasheet, MB90F543GSPF-GS pinout, MB90F543GSPF-GS application, or MB90F543GSPF-GS equivalent, this device supports dual CAN bus arbitration, 8/10-bit 8-channel ADC (26.3 µs conversion), 16-bit I/O timers with 8-input capture/4-output compare, and full-duplex UART0/UART1 with synchronous/asynchronous modes up to 2 Mbps - all critical for ECU firmware development and functional safety–aligned designs.

Technical Context

The MB90F543GSPF-GS implements the proprietary F2MC-16LX CPU core with 32-bit accumulator, 23 addressing modes, and enhanced C-language support including barrel shift, RETI, and system stack pointer. Its dual CAN controllers each support 16 message buffers with mixed mailbox/FIFO configuration and automatic retransmission on error.

Peripheral integration includes two independent UARTs (SCI), extended I/O serial interface, four 8/16-bit PPG timers, dual 16-bit reload timers, one 16-bit free-run timer, and an 8-channel A/D converter with selectable 8-/10-bit resolution and external trigger start - enabling tightly coupled sensor acquisition and actuator control without CPU intervention.

Key Specifications

Pinout & Package

LQFP-100 package with 0.5 mm lead pitch and exposed thermal pad; pin functions validated per Cypress Document 002-07696 Rev. *B (Pages 7–8). Pin numbering follows standard top-view orientation with corner pin 1 marked.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit automotive microcontroller applications.

Compared with RH850/F1L and TC1766, the MB90F543GSPF-GS offers optimal balance of dual CAN 2.0B bandwidth, Flash update flexibility, and thermal robustness in compact LQFP-100 - making it ideal for cost-sensitive, non-safety-critical automotive body electronics where pin count and code size efficiency matter most.

Availability

MB90F543GSPF-GS is available at Aetrix Electronics and suitable for automotive body control units, industrial CAN gateways, commercial telematics modules, and off-highway equipment controllers requiring stable component supply across extended temperature and long product lifecycles.

Supply support for MB90F543GSPF-GS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs high-reliability microcontrollers and analog ICs for automotive, industrial, and IoT applications, with emphasis on integrated connectivity and functional safety.

The MB90540G/545G series was developed specifically for automotive electronic control units needing dual CAN 2.0B interfaces, Flash-based field-upgradable firmware, and mixed-signal peripherals - targeting body electronics, gateway, and telematics segments.

FAQ

Does MB90F543GSPF-GS support CAN FD?

No. The MB90F543GSPF-GS implements FULL-CAN compliant with ISO 11898-1:2003 (CAN 2.0A/B only), supporting up to 1 Mbps bit rate and 11-/29-bit identifiers. It lacks CAN FD features such as flexible data-rate switching, extended payload length, and CRC enhancements. For CAN FD, consider Infineon's AURIX™ or RH850/F1L families.

What is the maximum operating frequency and corresponding instruction speed?

The MB90F543GSPF-GS achieves a maximum system clock of 16 MHz using its on-chip PLL ×4 multiplier with a 4 MHz crystal input. At this frequency and V_CC = 5.0 V, the minimum instruction execution time is 62.5 ns - verified in Cypress Document 002-07696 Rev. *B, Page 2. No overclocking beyond 16 MHz is supported.

How is Flash memory protected during over-the-air updates?

Flash protection uses hardware-enforced block locking activated by external programming voltage (V_PP) applied to dedicated pins. Each 128-byte block can be individually erased and written; boot sector protection prevents accidental overwrite of reset vector. Erase-suspend/resume commands allow interruption and resumption of background Flash operations without data loss.

Can the 32 kHz sub-clock operate independently during Stop mode?

Yes. In Stop mode, the main oscillator halts but the 32 kHz sub-clock remains active to drive the watchdog timer, real-time clock functions, and wake-up interrupt sources. This allows low-power periodic wake-up for sensor polling or CAN bus activity detection while consuming <10 µA - confirmed in Section 1.3 (Low-power consumption mode) of the datasheet.