Infineon Technologies MB90F543PF-G

Overview

MB90F543PF-G from Cypress Semiconductor is a 16-bit F2MC-16LX microcontroller with dual FULL-CAN 2.0A/B interfaces, 128 KB Flash ROM, 6 KB RAM, and QFP-100 package - designed for automotive body control modules requiring real-time CAN communication, deterministic interrupt response (34 sources, 8 priority levels), and mixed-signal integration including 8-channel 10-bit ADC (26.3 µs conversion) and programmable pulse generators.

For engineers reviewing the MB90F543PF-G datasheet, MB90F543PF-G pinout, MB90F543PF-G application, or MB90F543PF-G equivalent, key selection criteria include dual-CAN timing compliance up to 1 Mbps, PLL-configurable 16 MHz system clock (62.5 ns min instruction time), Flash block protection with 10,000 erase cycles, and support for external bus expansion up to 16 Mbytes.

Technical Context

The MB90F543PF-G implements the F2MC-16LX CPU core with 23 addressing modes, 32-bit accumulator for extended precision arithmetic, and enhanced C-language support via system stack pointer and barrel shift instructions. Its dual CAN controllers operate independently with flexible mailbox/FIFO buffering and automatic retransmission on error.

Peripheral subsystems include four 8/16-bit PPG timers, eight 16-bit input capture channels, four 16-bit output compare units, two 16-bit reload timers, and dual UARTs (UART0/SCI) supporting synchronous/asynchronous transfer at up to 2 Mbps - all synchronized to the same PLL-derived system clock.

Key Specifications

Pinout & Package

MB90F543PF-G is housed in a 100-pin QFP (PQH100) package with 0.65 mm pitch, lead-free finish, and thermal pad-compatible footprint. Pin functions are validated per Cypress Document 002-07696 Rev. *B.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-CAN microcontroller applications.

Compared with S32K144 and RL78/F14, MB90F543PF-G delivers native dual-CAN 2.0B with hardware mailbox/FIFO flexibility and integrated 10-bit ADC - eliminating external components in mid-tier automotive ECUs where CAN FD is unnecessary but dual-bus redundancy is mandatory.

Availability

MB90F543PF-G is available at Aetrix Electronics and suitable for automotive body control units, industrial CAN gateways, engine control subsystems, and off-highway vehicle telematics requiring stable component supply across extended temperature and long product lifecycles.

Supply support for MB90F543PF-G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs high-reliability microcontrollers and analog ICs for automotive, industrial, and IoT applications, with emphasis on functional safety and long-term supply stability.

The MB90540G/545G series was developed specifically for automotive body electronics and industrial control systems needing dual-CAN 2.0A/B compliance, Flash-based field-upgradable firmware, and mixed-signal integration without external support chips.

FAQ

What is the maximum CAN bit rate supported by MB90F543PF-G?

The MB90F543PF-G supports CAN 2.0A/B up to 1 Mbps in standard and extended frame formats. This maximum rate is achievable with proper bus termination, transceiver selection (e.g., TJA1050), and oscillator stability - confirmed in Section 29 (CAN Controller) of Document 002-07696 Rev. *B, where timing parameters for 1 Mbps arbitration and data phases are explicitly specified.

Does MB90F543PF-G support in-system programming of Flash memory?

Yes - MB90F543PF-G supports full in-system programming via its embedded Flash algorithm, enabling Write, Erase, Erase-Suspend, and Erase-Resume commands executed from RAM. A dedicated completion flag and block-level protection controlled by external Vpp voltage ensure safe field updates without external programmers, as detailed in Section 5 (Flash Memory) of the datasheet.

How many interrupt priority levels does the F2MC-16LX core provide?

The F2MC-16LX core in MB90F543PF-G implements 8 fixed hardware priority levels across 34 interrupt sources, including CAN transmit/receive/error, UART, ADC end-of-conversion, timer overflows, and external edge/level triggers. Priority assignment is non-maskable per level and defined in the Interrupt Map (Section 35) of the datasheet.

Is the 32 kHz sub-clock source internal or external?

The 32 kHz sub-clock is generated by an internal low-power oscillator circuit and does not require an external crystal. It drives the watch mode and real-time clock functions independently of the main 4 MHz crystal, enabling ultra-low-power wake-up intervals while preserving system state - verified in Section 1 (Features) and Electrical Characteristics (Page 37) of Document 002-07696 Rev. *B.