Infineon Technologies MB90F548GSPMC-G

Overview

MB90F548GSPMC-G from Cypress Semiconductor is a 16-bit F2MC-16LX microcontroller with dual FULL-CAN interfaces (CAN 2.0A/B), 128 KB Flash ROM, 4 KB RAM, and 81 general-purpose I/O ports. It operates at up to 16 MHz system clock (via on-chip PLL ×4), achieves 62.5 ns minimum instruction execution time, and targets automotive body control modules requiring CAN-based distributed ECU communication.

For engineers reviewing the MB90F548GSPMC-G datasheet, MB90F548GSPMC-G pinout, MB90F548GSPMC-G application, or MB90F548GSPMC-G equivalent, key selection considerations include dual-CAN timing determinism, Flash reprogrammability in-system, 10-bit A/D conversion across 8 channels with 26.3 µs per channel, and support for external bus expansion up to 16 Mbytes.

Technical Context

The MB90F548GSPMC-G implements the F2MC-16LX CPU core with 23 addressing modes, 32-bit accumulator for extended precision arithmetic, and enhanced C-language support via system stack pointer and barrel shift instructions. Its interrupt subsystem delivers 8 priority levels and 34 interrupt sources including EI2OS-triggered service and delayed task-switching requests.

Dual FULL-CAN controllers operate independently at up to 1 Mbps, each supporting flexible mailbox/FIFO message buffering, automatic retransmission on error, and programmable acceptance filtering (full-bit compare/mask or two partial masks). The peripheral set includes four 8/16-bit PPG timers, dual 16-bit reload timers, eight input capture channels, and four output compare channels-all synchronized to the same system clock domain.

Key Specifications

Pinout & Package

LQFP-100 package with 0.5 mm lead pitch, 14 mm × 14 mm body, and exposed thermal pad (non-electrical). Pin 1 marked by dot; pins numbered counterclockwise from top-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-CAN microcontroller applications.

Compared with RH850/F1L and S912ZVMC12F0, the MB90F548GSPMC-G uniquely provides dual classical CAN with full mailbox/FIFO flexibility, external bus expansion for legacy protocol bridging, and PLL-integrated clock synthesis - making it optimal for mid-tier automotive ECUs requiring deterministic dual-network coordination without architectural overhaul.

Availability

MB90F548GSPMC-G is available at Aetrix Electronics and suitable for automotive body electronics, electronic parking brake systems, and engine thermal management modules requiring stable component supply across extended product lifecycles.

Supply support for MB90F548GSPMC-G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs high-reliability microcontrollers and mixed-signal ICs for automotive, industrial, and IoT applications.

The MB90540G/545G series was developed specifically for automotive body electronics requiring dual-CAN networking, Flash-based field-upgradability, and extended temperature operation - emphasizing functional safety readiness and long-term supply stability.

FAQ

Does MB90F548GSPMC-G support CAN FD?

No. The MB90F548GSPMC-G implements two FULL-CAN controllers compliant exclusively with ISO 11898-1 (CAN 2.0A/B), supporting data rates up to 1 Mbps with standard 11-bit or extended 29-bit identifiers. It does not support CAN FD's variable bit rate, larger payload, or CRC enhancements. For CAN FD requirements, consider Infineon's AURIX TC3xx family.

What is the maximum external memory address space supported?

The MB90F548GSPMC-G supports up to 16 Mbytes of external memory via its multiplexed 16-bit address/data bus. Address lines A0–A23 are available on port pins P20–P27 and P30–P37, with ALE, RD, WR, HRQ, and HAK signals enabling glueless connection to SRAM, EPROM, or FPGA peripherals without external address latches.

How is Flash programming performed in-system?

Flash programming uses on-chip embedded algorithms: Write, Erase, Erase-Suspend, and Erase-Resume commands executed via dedicated registers. A completion flag indicates operation status, and block-level protection is enforced using externally applied Vpp (12.5 V). No external programmer is required - updates can be triggered via CAN or UART using customer-defined bootloader code.

Is the 32 kHz sub-clock generated internally or externally?

The 32 kHz sub-clock is generated externally using a dedicated 32.768 kHz crystal connected to X0/X1 pins. This oscillator feeds the watch-mode timer and real-time clock functions independently of the main PLL system clock, enabling ultra-low-power wake-up capability while the CPU and main oscillator remain halted.