Infineon Technologies MB91F365GBPMT-G-N2E1

Overview

MB91F365GBPMT-G-N2E1 from Infineon Technologies is a 32-bit FR family microcontroller featuring 512 KB on-chip Flash memory, 48 KB RAM, and integrated CAN 2.0B controller with three channels. It operates at up to 60 MHz, supports IEEE 1149.1 JTAG debugging, and targets automotive body control modules requiring real-time I/O handling and communication robustness.

For engineers reviewing the MB91F365GBPMT-G-N2E1 datasheet, MB91F365GBPMT-G-N2E1 pinout, MB91F365GBPMT-G-N2E1 application, or MB91F365GBPMT-G-N2E1 equivalent, key selection criteria include CAN channel count, Flash endurance (100k write/erase cycles), operating temperature range (–40°C to +125°C), and LQFP-120 package compatibility with automotive PCB layout constraints.

Technical Context

This MCU implements Fujitsu's FR architecture with 32-bit data path and 24-bit address space, supporting both little-endian and big-endian operation modes. It integrates a 16-channel 10-bit ADC, 32-bit watchdog timer with window function, and dual CAN controllers sharing one message RAM for synchronized message filtering.

The device uses a multi-layer bus architecture with separate instruction and data buses (Harvard-style), enabling simultaneous fetch and execution. Its clock system includes PLL-based frequency multiplication, internal RC oscillator (1 MHz), and external crystal support up to 20 MHz for precise timing in ECU synchronization tasks.

Key Specifications

Pinout & Package

MB91F365GBPMT-G-N2E1 is housed in a 120-pin LQFP package with 0.4 mm lead pitch and thermally enhanced exposed pad for ECU-level heat dissipation. Pin functions are organized into dedicated groups: power (VDD, VSS), clock (XIN/XOUT), CANH/CANL (three sets), ADC inputs (AN0–AN15), and general-purpose I/O with programmable pull-up/down and slew-rate control.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit automotive microcontroller applications.

Compared with R7F7010233AFP#AA0, MB91F365GBPMT-G-N2E1 delivers higher real-time determinism via FR architecture and triple CAN for distributed node consolidation; versus S32K144WHT0MLHT, it offers lower static current and simpler qualification path for non-gateway body modules.

Availability

MB91F365GBPMT-G-N2E1 is available at Aetrix Electronics and suitable for automotive body control modules, door control units, roof control modules, and seat control units requiring stable component supply under AEC-Q100 qualification.

Supply support for MB91F365GBPMT-G-N2E1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global manufacturing and R&D centers.

The MB91F365 series belongs to Infineon's legacy FR-family automotive MCU line, designed specifically for cost-optimized, high-reliability body electronics where CAN network scalability and Flash longevity are critical.

FAQ

What is the maximum operating frequency of the MB91F365GBPMT-G-N2E1?

The MB91F365GBPMT-G-N2E1 operates at a maximum CPU frequency of 60 MHz, achieved using its on-chip PLL with external crystal input up to 20 MHz. This frequency is fully supported across the full –40°C to +125°C temperature range and meets AEC-Q100 Grade 2 specifications for automotive use.

Does this MCU support CAN FD or only classical CAN?

The MB91F365GBPMT-G-N2E1 supports only classical CAN 2.0B (up to 1 Mbps), not CAN FD. Its three CAN controllers implement standard arbitration, error framing, and message filtering per ISO 11898-1, with no support for flexible data-rate payloads or extended bit timing configurations.

Is the 512 KB Flash memory organized in uniform sectors or mixed block sizes?

The 512 KB Flash is divided into 16 KB main blocks and eight 2 KB boot blocks, each independently erasable. Sector erase times are 10 ms per 16 KB block and 5 ms per 2 KB block, enabling efficient firmware updates and bootloader partitioning without full-chip erase.

What debug interface does MB91F365GBPMT-G-N2E1 provide?

The device provides full IEEE 1149.1 JTAG interface with TRST, TDI, TDO, TMS, and TCK pins. It supports boundary-scan testing, flash programming, and real-time debugging via standard JTAG emulators compatible with Fujitsu FR architecture toolchains.