Infineon Technologies MB91F525FSCPMC-GS-ERE2

Overview

MB91F525FSCPMC-GS-ERE2 from Infineon Technologies (formerly Cypress) is a 32-bit FR81S microcontroller for automotive applications, featuring an 80 MHz CPU, 768 + 64 KB program flash, 96 KB main RAM + 8 KB backup RAM, IEEE 754-compliant FPU, and integrated CAN 2.0B controllers (3 channels, up to 1 Mbps). It operates across −40 °C to +125 °C with 5 V supply and supports LIN 2.1, I²C, UART, CSIO, and 12-channel multi-function serial interfaces.

For engineers reviewing the MB91F525FSCPMC-GS-ERE2 datasheet, MB91F525FSCPMC-GS-ERE2 pinout, MB91F525FSCPMC-GS-ERE2 application, or MB91F525FSCPMC-GS-ERE2 equivalent, key selection criteria include its 100-pin LQFP package, sub-oscillator support, hardware watchdog, memory protection unit (MPU), and dual A/D converter units totaling 48 channels at 12-bit resolution with 1.4 µs conversion time.

Technical Context

The MB91F525FSCPMC-GS-ERE2 implements the FR81S 32-bit RISC core with 5-stage pipeline, Harvard architecture, and instruction compatibility with the FR family. It integrates on-chip PLL clock multiplication (1×–20×) from 4–16 MHz main oscillator or 32 kHz sub-oscillator, plus a 100 kHz CR oscillator for fail-safe clock switching.

Peripheral subsystems include three independent CAN controllers (128/64 message buffers per channel), dual 12-bit A/D converters (max 48 ch total), two 8-bit D/A outputs, RTC with subclock calibration, and 16-bit PPG/timer resources supporting LED drive, waveform generation, and input capture/output compare with 32-bit cascade capability.

Key Specifications

Pinout & Package

MB91F525FSCPMC-GS-ERE2 is housed in a 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) package with exposed thermal pad. Pin functions are defined per the CY91520 Series datasheet Rev. *I, Section 2 (Pin Assignment) and Section 3 (Pin Description).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit automotive microcontroller applications.

Compared with RH850/F1K and S32K144, MB91F525FSCPMC-GS-ERE2 uniquely combines 3 CAN 2.0B channels, LIN 2.1, IEEE 754 FPU, and 48-channel A/D in a single 100-pin LQFP - making it optimal for cost-sensitive, high-channel-count automotive body and powertrain nodes requiring mixed-network interoperability and embedded math acceleration.

Availability

MB91F525FSCPMC-GS-ERE2 is available at Aetrix Electronics and suitable for engine control units, body control modules, ADAS sensor hubs, and electric power steering systems requiring stable component supply across automotive production lifecycles.

Supply support for MB91F525FSCPMC-GS-ERE2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive MCUs, and security solutions, with global R&D and manufacturing infrastructure.

The CY91520 series - now part of Infineon's automotive MCU portfolio - was originally developed by Cypress to address cost-sensitive, high-reliability 32-bit control applications in powertrain, chassis, and body electronics with integrated analog and communication peripherals.

FAQ

What is the maximum operating frequency and associated instruction cycle time?

The MB91F525FSCPMC-GS-ERE2 achieves a maximum CPU frequency of 80 MHz using its on-chip PLL with 4.0 MHz crystal input multiplied by 20. This yields a minimum instruction execution time of 12.5 ns per cycle, confirmed in the CY91520 Series datasheet Rev. *I, Section 1. Product Lineup. The FR81S core executes most instructions in a single cycle due to its 5-stage pipeline and load/store architecture.

Does this MCU support functional safety standards such as ISO 26262?

Yes - the MB91F525FSCPMC-GS-ERE2 includes hardware features aligned with ASIL-B requirements: memory ECC (flash and RAM), lockstep-capable MPU with eight protection regions, hardware watchdog timer, CRC generator, and timing protection unit (TPU). While Infineon provides safety documentation (e.g., FMEDA reports), final ASIL classification depends on system-level integration and diagnostic coverage implementation per ISO 26262-5.

How many CAN message buffers are allocated per channel, and are they configurable?

CAN channel 0 provides 128 message buffers (64 transmit + 64 receive), while channels 1 and 2 each provide 64 buffers (32 transmit + 32 receive). These allocations are fixed in hardware and cannot be redistributed across channels. Buffer usage is managed via the CAN controller's message object RAM and acceptance filtering logic, as detailed in Section 11.3 of the datasheet.

Is the 32.768 kHz sub-oscillator supported, and what RTC features depend on it?

Yes - the MB91F525FSCPMC-GS-ERE2 supports external 32.768 kHz crystal connection via RTCXIN/RTCXOUT pins. The RTC uses this sub-oscillator for accurate timekeeping (days/hours/minutes/seconds), and its calibration function adjusts the main-to-sub clock ratio via prescaler settings. Sub-oscillator failure triggers automatic switch to the 100 kHz CR oscillator, preserving RTC operation during quartz faults.