Infineon Technologies MB91F526DSDPMC-GSE1

Overview

MB91F526DSDPMC-GSE1 from Cypress Semiconductor is a 32-bit FR81S automotive microcontroller in the MB91520 series, featuring an 80 MHz CPU, 1024+64 KB program flash, 128 KB main RAM + 8 KB backup RAM, IEEE754-compliant FPU, and triple CAN 2.0B controllers. It targets engine control units and body electronics requiring real-time deterministic execution, fault-tolerant communication, and extended temperature operation.

For engineers reviewing the MB91F526DSDPMC-GSE1 datasheet, MB91F526DSDPMC-GSE1 pinout, MB91F526DSDPMC-GSE1 application, or MB91F526DSDPMC-GSE1 equivalent, this part supports LIN 2.1, UART/CSIO/I²C multi-serial interfaces, 48-channel PPG for LED/actuator timing, 12-bit ADC (up to 48 ch), and hardware watchdog with dual LVD monitoring - critical for ASIL-B–capable automotive subsystems.

Technical Context

The MB91F526DSDPMC-GSE1 implements the FR81S 5-stage pipelined RISC core with 16×32-bit GPRs, 16 priority-level interrupt controller, and Harvard architecture enabling concurrent instruction fetch and data access. It integrates memory protection (MPU) with eight configurable regions and privilege/user mode access control.

Its peripheral set includes three independent CAN controllers (1 Mbps max, 128/64 msg buffers per channel), 12-bit successive-approximation ADC (1.4 μs conversion), dual 8-bit D/A converters, RTC with subclock calibration, and SSCG-based clock generation supporting 4–16 MHz main oscillation and 32 kHz sub-oscillation with automatic CR fallback on failure.

Key Specifications

Pinout & Package

MB91F526DSDPMC-GSE1 is housed in a 80-pin LQFP package (LQH080) with exposed thermal pad, RoHS-compliant, moisture sensitivity level 3. Pin functions include dedicated CANH/CANL, LIN TX/RX, multiple I/O groups with programmable pull-up/down, and dedicated debug (OCD) pins.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit automotive microcontroller applications.

Compared with RH850/F1L and S32K144, MB91F526DSDPMC-GSE1 delivers higher deterministic throughput (80 MHz FR81S), integrated PPG for hardware-timed actuation, and triple legacy CAN - making it optimal for cost-constrained yet performance-demanding ASIL-B ECUs where CAN FD is not required.

Availability

MB91F526DSDPMC-GSE1 is available at Aetrix Electronics and suitable for engine control units, body control modules, ADAS sensor hubs, and electric power steering systems requiring stable component supply across automotive production lifecycles.

Supply support for MB91F526DSDPMC-GSE1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs high-reliability microcontrollers and mixed-signal ICs for automotive, industrial, and IoT applications, with emphasis on functional safety and long-term supply stability.

The MB91520 series was engineered specifically for ASIL-B automotive subsystems - integrating safety mechanisms (MPU, ECC, dual LVD, hardware CRC), extended temperature operation, and multi-protocol connectivity without external co-processors.

FAQ

What is the maximum operating frequency and minimum instruction cycle time of the MB91F526DSDPMC-GSE1?

The MB91F526DSDPMC-GSE1 operates at a maximum frequency of 80 MHz, delivering a minimum instruction execution time of 12.5 ns. This is achieved using the on-chip PLL with 20× multiplication of a 4.0 MHz crystal source. The FR81S core's 5-stage pipeline and 16-bit fixed-length instruction set ensure consistent single-cycle execution for basic operations.

Does MB91F526DSDPMC-GSE1 support CAN FD or only classical CAN 2.0B?

The MB91F526DSDPMC-GSE1 supports only Classical CAN 2.0B across its three independent controllers, with bit rates up to 1 Mbps. It does not implement CAN FD features such as flexible data-rate or extended payload length. Its CAN blocks are fully compliant with ISO 11898-1:2003 and support message buffering (128/64/64 slots) and mailbox prioritization.

How is the 128 KB RAM organized, and what is the purpose of the 8 KB backup RAM?

The 128 KB RAM is main SRAM used for program stack, heap, and real-time data buffers. The separate 8 KB backup RAM is powered by VBAT and retains data during Stop/Watch modes and ignition-off states. It stores critical parameters like odometer values, calibration offsets, and security keys - accessible immediately upon wake-up without reinitialization.

Is the MB91F526DSDPMC-GSE1 qualified for automotive AEC-Q100 Grade 1 or Grade 0?

The MB91F526DSDPMC-GSE1 is qualified to AEC-Q100 Grade 1 (−40 °C to +125 °C), as confirmed in Cypress's official qualification report 002-04662 Rev. *F. It is not rated for Grade 0 (−40 °C to +150 °C). The device meets all stress tests including HTOL, TC, UHAST, and ESD per AEC-Q100 Rev. G, with full documentation available in the manufacturer's qualification summary.