Infineon Technologies MB96F355RSBPMC1-GSE2

Overview

MB96F355RSBPMC1-GSE2 from Fujitsu Semiconductor is a 16-bit F2MC-16FX microcontroller with 288KB Flash, 12KB RAM, dual CAN 2.0A/B interfaces (ISO16845 certified), and up to 56MHz CPU operation via on-chip PLL. It features 15-channel 10-bit SAR ADC, 4 USARTs (SCI/LIN), 2 I²C channels, real-time clock, and 20-channel programmable pulse generator - deployed in automotive body control modules requiring deterministic timing and CAN-based networked diagnostics.

For engineers reviewing the MB96F355RSBPMC1-GSE2 datasheet, MB96F355RSBPMC1-GSE2 pinout, MB96F355RSBPMC1-GSE2 application, or MB96F355RSBPMC1-GSE2 equivalent, key selection criteria include dual-CAN support with FIFO mode, flash security and sector protection, 13 low-power operating modes, clock modulation for EMI reduction, and external bus interface with 6 chip selects for memory expansion.

Technical Context

The MB96F355RSBPMC1-GSE2 implements Fujitsu's F2MC-16FX core with instruction pipeline and 23 addressing modes, enabling RISC-like performance at 56MHz (17.8ns min instruction cycle). Its clock tree supports independent domain configuration: CPU clock sourced from PLL (x1–x25) or external oscillator, while peripherals select from main clock, subclock (32–100kHz), or 100kHz/2MHz internal RC oscillator.

System-level integration includes two ISO16845-certified CAN controllers (32 message objects each, programmable FIFO/loopback modes), four full-duplex USARTs with LIN master/slave capability, and a 10-bit SAR ADC with software/external trigger and continuous conversion modes - all managed via a centralized interrupt controller with 8 priority levels and NMI.

Key Specifications

Pinout & Package

MB96F355RSBPMC1-GSE2 is housed in a 64-pin plastic LQFP (M23/M24 package) with 0.5 mm lead pitch and exposed thermal pad. Pin functions are validated per Fujitsu FME-MB96350 rev 7 datasheet and include dedicated CANH/CANL, USART TX/RX/SCK lines, ADC analog inputs (AN0–AN14), and multiplexed external bus signals (AD00–AD15, A16–A21, CS0_R–CS5_R).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit automotive microcontroller applications.

Compared with R5F100LEAFB#30 and SPC560P50L5, MB96F355RSBPMC1-GSE2 uniquely balances dual-CAN, external bus support, integrated voltage regulation, and flash security in a mature 16-bit platform - making it optimal for cost-constrained, safety-aware automotive body electronics where design reuse and long-term supply stability are critical.

Availability

MB96F355RSBPMC1-GSE2 is available at Aetrix Electronics and suitable for automotive body control modules, industrial CAN gateways, smart lighting controllers, and diagnostic communication controllers requiring stable component supply across extended production lifecycles.

Supply support for MB96F355RSBPMC1-GSE2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Fujitsu Semiconductor (now part of Socionext Inc. since 2017) designed high-reliability microcontrollers for automotive, industrial, and consumer applications with emphasis on low-power operation and functional safety.

The MB96350 Series targets automotive body electronics and industrial control systems requiring dual-CAN connectivity, deterministic real-time response, and long-lifecycle component assurance - built on the proven F2MC-16FX architecture.

FAQ

What is the maximum operating frequency and corresponding instruction cycle time?

The MB96F355RSBPMC1-GSE2 achieves a maximum CPU clock of 56 MHz using its on-chip PLL, resulting in a minimum instruction cycle time of 17.8 nanoseconds. This timing is confirmed in the FME-MB96350 rev 7 datasheet Section 1.2 and verified by the 23-bit main clock timer specification supporting 56 MHz input.

Does this MCU support LIN communication, and if so, how is it implemented?

Yes, the MB96F355RSBPMC1-GSE2 supports LIN 2.0/2.1 via its four full-duplex USARTs configured in LIN mode. Each USART can operate as master or slave, with dedicated hardware for header generation, checksum calculation, and response timing - documented in Section 5.4.2 of the datasheet and validated by LIN conformance testing in Fujitsu's Customer Design Review Supplement.

How many CAN message objects are supported, and are they shared between channels?

The device provides two independent CAN controllers, each with 32 dedicated message objects - totaling 64 non-overlapping buffers. Each object has its own identifier mask and acceptance filtering logic; no sharing occurs between CAN0 and CAN1, enabling concurrent operation on separate networks without resource contention.

Is external memory expansion supported, and what interface signals are available?

Yes, the MB96F355RSBPMC1-GSE2 includes a full external bus interface with 16-bit bidirectional data (AD00–AD15), 24-bit address capability (A16–A21 plus AD00–AD15 multiplexing), six chip select outputs (CS0_R–CS5_R), and wait-state control. This allows direct connection to SRAM, NOR Flash, or peripheral ASICs - detailed in Section 12.1 of the FME-MB96350 datasheet.