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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Asahi Kasei Microdevices/AKM AK1110AEU50

Name: AK1110AEU50
Brand: Asahi Kasei Microdevices/AKM
SKU: AK1110AEU50
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AK1110AEU50

Manufacturer:: Asahi Kasei Microdevices/AKM

Category:: Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Package:: 10-UFDFN Exposed Pad

Datasheet:: AK1110AEU50.pdf

Description:: IC REG LINEAR 5V/5V 220MA 10PLP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AK1110AEU50 from Asahi Kasei Microdevices is a dual-output low-dropout linear regulator with independent 5.0 V outputs (LDO1: 200 mA, LDO2: 100 mA), 600 mV dropout at full load, ultra-low output noise (2 µV_RMS and 1 µV_RMS), and high PSRR (83 dB and 100 dB at 1 kHz). It serves as a precision power supply for noise-sensitive analog/RF circuitry in compact embedded systems.

For engineers reviewing the AK1110AEU50 datasheet, AK1110AEU50 pinout, AK1110AEU50 application, or AK1110AEU50 equivalent, key selection criteria include dual-rail ultra-low-noise regulation, NP-pin bypass capability for noise suppression, thermal/overcurrent protection, and PLP10-2725 package compatibility with space-constrained PCB layouts.

Technical Context

The AK1110AEU50 integrates two independent bipolar LDO regulators sharing a common ground plane but featuring separate input, output, and noise-bypass terminals. Each channel includes dedicated internal protection circuits-thermal shutdown at 135–155 °C and current limiting-with autonomous recovery behavior.

Its monolithic silicon bipolar architecture enables stable operation with ceramic capacitors ≥3.3 µF and supports noise optimization via external 3.3 µF+ capacitors on NP_LDO1/NP_LDO2 pins-bypass paths that do not affect loop stability but directly suppress 10 Hz–100 kHz output noise and improve PSRR above 1 kHz.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Voltage	5.0 V ±100 mV (LDO1/LDO2); maintains accuracy across –40°C to +85°C ambient and 1–200 mA / 1–100 mA loads.
Dropout Voltage	600 mV at 200 mA (LDO1), 600 mV at 100 mA (LDO2); enables regulation down to VIN = 5.6 V while sustaining full rated output.
Output Noise	2 µV_RMS (LDO1), 1 µV_RMS (LDO2), 10 Hz–100 kHz; measured with 10 µF NP capacitor; critical for DAC reference and PLL VCO supply rails.
PSRR	83 dB @ 1 kHz (LDO1), 100 dB @ 1 kHz (LDO2); ensures rejection of switching noise from upstream DC/DC converters.
Enable Threshold	VENH ≥ 1.8 V (ON), VENL ≤ 0.35 V (OFF); built-in 300 kΩ pull-down enables simple microcontroller GPIO control without external biasing.
Thermal Protection	Shuts down at T_J = 135–155 °C; auto-recovers when junction cools below hysteresis threshold-no latch-up or manual reset required.
Package	PLP10-2725 (2.7 mm × 2.5 mm × 0.6 mm) with exposed thermal pad internally connected to GND; supports JEDEC-compliant 4-layer board thermal derating (55.4 °C/W).

Pinout & Package

AK1110AEU50 uses the PLP10-2725 10-pin leadless package with an exposed thermal pad (internally tied to GND). Pin 1–10 are arranged in a single row; the exposed pad must be soldered to a large PCB GND plane using ≥4 thermal vias for optimal thermal performance and EMI suppression.

Pin/Terminal	Circuit Role	Design Meaning
VOUT_LDO2	LDO2 regulated output	Delivers stable 5.0 V / 100 mA; requires local 3.3 µF+ ceramic capacitor to GND_LDO2 for stability and transient response.
VIN_LDO2	LDO2 input power	Accepts 6–14 V input; decoupled by shared CIN (≥1.0 µF) near VIN_LDO1/VIN_LDO2 pins and GND_REG.
EN	Global enable control	High-active logic input (1.8–16 V compatible); controls both LDO1 and LDO2 simultaneously; internal 300 kΩ pull-down ensures safe OFF state at power-up.
VIN_LDO1	LDO1 input power	Accepts same 6–14 V input as VIN_LDO2; shares CIN but must maintain low-impedance path to GND_REG.
VOUT_LDO1	LDO1 regulated output	Delivers stable 5.0 V / 200 mA; higher current capability than LDO2; requires dedicated COUT1 ≥3.3 µF with ESR ≤0.1 Ω.
GND_LDO1	LDO1 ground return	Separate ground pin for LDO1 output stage; routed independently to minimize noise coupling into sensitive analog loads.
NP_LDO1	LDO1 noise bypass	Connects to external 3.3 µF+ capacitor to GND_LDO1; reduces 10 Hz–100 kHz output noise without affecting stability-key for RF/PLL applications.
GND_REG	Internal regulator ground	Reference ground for internal bias circuitry; must be tied to system GND plane with low-inductance connection.
NP_LDO2	LDO2 noise bypass	Same function as NP_LDO1 but for LDO2; enables independent noise tuning per rail-critical when powering mixed-signal SoCs with distinct analog/digital domains.
GND_LDO2	LDO2 ground return	Separate ground pin for LDO2; prevents LDO2 load transients from modulating LDO1 output voltage via shared ground impedance.

Key Features

Feature	Design Value
Dual independent LDOs	Enables clean, isolated 5.0 V supplies for analog (LDO2) and digital/IO (LDO1) domains-eliminates need for two discrete regulators and saves board area.
Ultra-low noise (1–2 µV_RMS)	Meets stringent requirements for high-resolution DAC references and VCO power rails where sub-µV noise directly impacts SNR and phase jitter.
High PSRR (83–100 dB)	Rejects ripple from noisy switchers (e.g., buck converters) up to 1 MHz-ensures signal integrity in RF front-ends and ADC clocking circuits.
NP-terminal noise bypass	Allows designers to trade off capacitor count vs. noise floor: adding 3.3 µF+ to NP pins improves noise/PSRR without altering output capacitor selection or stability margins.
Thermal + overcurrent protection	Self-protecting operation under overload or poor heatsinking-prevents field failures in sealed enclosures or high-ambient industrial environments.

Applications

High-Precision DAC Power	RF Transceiver Bias
Use Scenario: Powering 16-bit+ DACs in test equipment or medical imaging systems where supply-induced distortion degrades SFDR. IC Role / Device Role / Timing Role: Provides ultra-low-noise 5.0 V reference rail for DAC analog section; LDO2 used for core, LDO1 for digital interface. Use Value: 1 µV_RMS noise on LDO2 minimizes code-dependent spurs; NP_LDO2 capacitor further suppresses 1/f noise critical for DC-accurate outputs.	Use Scenario: Supplying LNA, mixer, and VCO stages in sub-GHz ISM-band radios where supply ripple causes reciprocal mixing and phase noise degradation. IC Role / Device Role / Timing Role: Delivers quiet 5.0 V to VCO tuning port and LNA collector; LDO1 powers digital control logic, LDO2 powers analog signal chain. Use Value: 100 dB PSRR at 1 kHz rejects PA switching noise coupled through shared PCB traces; NP_LDO2 capacitor extends PSRR benefit to 100 kHz.
PLL Clock Generator Supply	FPGA I/O Bank Regulation
Use Scenario: Powering PLL charge pump and VCO in clock synthesizers where supply noise translates directly to integrated jitter. IC Role / Device Role / Timing Role: Supplies dedicated 5.0 V rail to PLL analog core; LDO2 selected for lowest noise, LDO1 for auxiliary logic. Use Value: 2 µV_RMS noise on LDO1 (with NP_LDO1 cap) reduces 12-kHz–20-MHz jitter contribution by >3 dB versus standard LDOs-improving RMS jitter spec.	Use Scenario: Regulating 5.0 V I/O banks on Xilinx Artix-7 or Intel MAX 10 FPGAs requiring stable voltage during fast slew-rate data transfers. IC Role / Device Role / Timing Role: Dual-rail LDO delivers 200 mA (LDO1) to high-drive banks and 100 mA (LDO2) to low-power banks-reducing inter-bank crosstalk. Use Value: Independent GND_LDO1/GND_LDO2 pins prevent simultaneous switching noise from corrupting adjacent bank timing margins-enabling reliable 100+ Mbps LVCMOS signaling.

High-Precision DAC Power

RF Transceiver Bias

Use Scenario: Powering 16-bit+ DACs in test equipment or medical imaging systems where supply-induced distortion degrades SFDR.

IC Role / Device Role / Timing Role: Provides ultra-low-noise 5.0 V reference rail for DAC analog section; LDO2 used for core, LDO1 for digital interface.

Use Value: 1 µV_RMS noise on LDO2 minimizes code-dependent spurs; NP_LDO2 capacitor further suppresses 1/f noise critical for DC-accurate outputs.

Use Scenario: Supplying LNA, mixer, and VCO stages in sub-GHz ISM-band radios where supply ripple causes reciprocal mixing and phase noise degradation.

IC Role / Device Role / Timing Role: Delivers quiet 5.0 V to VCO tuning port and LNA collector; LDO1 powers digital control logic, LDO2 powers analog signal chain.

Use Value: 100 dB PSRR at 1 kHz rejects PA switching noise coupled through shared PCB traces; NP_LDO2 capacitor extends PSRR benefit to 100 kHz.

PLL Clock Generator Supply

FPGA I/O Bank Regulation

Use Scenario: Powering PLL charge pump and VCO in clock synthesizers where supply noise translates directly to integrated jitter.

IC Role / Device Role / Timing Role: Supplies dedicated 5.0 V rail to PLL analog core; LDO2 selected for lowest noise, LDO1 for auxiliary logic.

Use Value: 2 µV_RMS noise on LDO1 (with NP_LDO1 cap) reduces 12-kHz–20-MHz jitter contribution by >3 dB versus standard LDOs-improving RMS jitter spec.

Use Scenario: Regulating 5.0 V I/O banks on Xilinx Artix-7 or Intel MAX 10 FPGAs requiring stable voltage during fast slew-rate data transfers.

IC Role / Device Role / Timing Role: Dual-rail LDO delivers 200 mA (LDO1) to high-drive banks and 100 mA (LDO2) to low-power banks-reducing inter-bank crosstalk.

Use Value: Independent GND_LDO1/GND_LDO2 pins prevent simultaneous switching noise from corrupting adjacent bank timing margins-enabling reliable 100+ Mbps LVCMOS signaling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output ultra-low-noise LDO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Torex XC6223D501MR-G	Single-output 5.0 V LDO (200 mA), no NP pin, 12 µV_RMS noise, 65 dB PSRR @ 1 kHz	Lacks dual-rail isolation and noise-bypass capability; suitable only when one clean rail suffices	Select if board space allows two separate ICs and noise budget permits 12× higher RMS noise.
Analog Devices ADM7150ACPZ-5.0-R7	Single-output 5.0 V LDO (800 mA), 0.9 µV_RMS noise, 70 dB PSRR @ 1 kHz, no enable or NP pin	Higher current but no dual output or EN control; requires external logic for sequencing	Choose when ultra-lowest noise is mandatory and system can accommodate discrete enable circuitry and larger 3 mm × 3 mm package.

Compared with XC6223D501MR-G and ADM7150ACPZ-5.0-R7, AK1110AEU50 uniquely integrates dual independent ultra-low-noise rails with NP-bypass and single-pin enable-reducing component count, PCB area, and design complexity for multi-domain analog systems.

Availability

AK1110AEU50 is available at Aetrix Electronics and suitable for high-precision DAC power, RF transceiver bias, PLL clock generator supply, and FPGA I/O bank regulation requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for AK1110AEU50 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Asahi Kasei Microdevices (AKM) is a Japanese semiconductor company specializing in analog, sensor, and mixed-signal ICs, with leadership in audio codecs, Hall-effect sensors, and precision power management solutions.

The AK1110AEU50 belongs to AKM's ultra-low-noise LDO family designed specifically for noise-critical analog subsystems in communications, instrumentation, and medical electronics-emphasizing PSRR, output noise, and thermal robustness over raw current density.

FAQ

What is the maximum allowable input voltage for AK1110AEU50?

The absolute maximum input voltage for AK1110AEU50 is 16 V across VIN_LDO1 and VIN_LDO2 pins. However, the recommended operating range is 6 V to 14 V per the datasheet. Exceeding 14 V risks accelerated parametric drift and reduced long-term reliability, especially at elevated temperatures. Always observe the 0.3 V reverse bias limit on VOUT pins relative to GND.

How does the NP_LDO1 and NP_LDO2 functionality differ between AK1110AEU50 and standard LDOs?

Unlike standard LDOs, AK1110AEU50 provides dedicated NP_LDO1 and NP_LDO2 pins that connect to internal noise-reduction circuitry-allowing external capacitors (≥3.3 µF) to shunt high-frequency noise before it reaches the output. This architecture achieves 1–2 µV_RMS noise without compromising stability or requiring ultra-low-ESR output capacitors, a capability absent in conventional single-rail LDOs.

Can AK1110AEU50 power both analog and digital sections of an ADC simultaneously?

Yes-AK1110AEU50 is explicitly designed for this use case. LDO2 (100 mA, 1 µV_RMS) powers noise-sensitive analog sections like reference buffers and front-end amplifiers, while LDO1 (200 mA, 2 µV_RMS) supplies digital interfaces and internal logic. Separate GND_LDO1/GND_LDO2 pins prevent digital switching noise from modulating the analog rail, preserving ENOB in 16-bit+ ADCs.

What thermal derating applies to AK1110AEU50 on a standard 2-layer PCB?

On a 2-layer PCB (not the JEDEC 4-layer reference), AK1110AEU50's thermal resistance rises significantly-derating exceeds –18 mW/°C above 25°C ambient. For continuous 200 mA operation, keep ambient below 60°C or add copper pour + thermal vias under the exposed pad. The datasheet specifies 55.4 °C/W only for compliant 4-layer boards; uncontrolled 2-layer layouts may exceed 100 °C/W.

Is AK1110AEU50 RoHS compliant and halogen-free?

Yes-AK1110AEU50 meets EU RoHS Directive 2011/65/EU and is halogen-free per J-STD-709. Asahi Kasei confirms compliance in its official product change notices and material declarations. No exemptions apply; lead content is <1000 ppm, and brominated flame retardants are absent from the PLP10-2725 package molding compound.

AK1110AEU50 Specifications

Product attributes: Attribute value

Manufacturer:: Asahi Kasei Microdevices/AKM

Series:: -

Package/Case:: 10-UFDFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Output Configuration:: Positive

Output Type:: Fixed

Number of Regulators:: 2

Voltage - Input (Max):: 14V

Voltage - Output (Min/Fixed):: 5V, 5V

Voltage - Output (Max):: -

Voltage Dropout (Max):: 0.6V @ 200mA, 0.6V @ 100mA

Current - Output:: 220mA

Current - Quiescent (Iq):: 5 mA

Current - Supply (Max):: 7 mA

PSRR:: 83dB ~ 70dB (1kHz ~ 1MHz), 100dB ~ 76dB (1kHz ~ 1MHz)

Control Features:: Enable

Protection Features:: Over Current, Thermal Shutdown

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 10-PLP-2725

AK1110AEU50 FAQ

1.How can I place an order for AK1110AEU50 through Aetrix?

Please submit a Request for Quotation (RFQ) for AK1110AEU50 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AK1110AEU50 reliable?

The price and inventory of AK1110AEU50 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AK1110AEU50 is usually 5 days.

3.What payment methods are accepted for AK1110AEU50?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AK1110AEU50 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AK1110AEU50?

AK1110AEU50 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AK1110AEU50 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AK1110AEU50?

For technical support, including AK1110AEU50 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AK1110AEU50 requirements.

6.How does Aetrix verify that AK1110AEU50 is sourced from the original manufacturer or authorized distributors?

All AK1110AEU50 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AK1110AEU50 meets industry standards.

7.What is the process for return or replacement of AK1110AEU50?

All AK1110AEU50 units undergo pre-shipment inspection (PSI). If there is an issue with AK1110AEU50, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AK1110AEU50 part is unused and in its original packaging.

Return procedure for AK1110AEU50:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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