Diodes Incorporated AP7362A-18SP-13
- Part No.:
- AP7362A-18SP-13
- Manufacturer:
- Diodes Incorporated
- Package:
- 8-SOIC (0.154", 3.90mm Width) Exposed Pad
- Datasheet:
-
AP7362A-18SP-13.pdf
- Description:
- LDO CMOS HICURR SO-8EP T&R 2.5K
- Quantity:
- Payment:

- Shipping:

Inventory:1,284
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Product details
Overview
AP7362A-18SP-13 from Diodes Incorporated is a 1.5A, ultra-low dropout linear regulator with fixed 1.8V output, EN control, 190mV dropout at full load, ±1.5% VADJ accuracy at +25°C, and stable operation with 10µF ceramic input/output capacitors. It serves as a core power supply for FPGA I/O rails in networking equipment such as routers and STBs.
For engineers reviewing the AP7362A-18SP-13 datasheet, AP7362A-18SP-13 pinout, AP7362A-18SP-13 application, or AP7362A-18SP-13 equivalent, key selection criteria include dropout voltage under 1.5A load, thermal shutdown threshold at +170°C, PSRR of 65dB at 120Hz, ground pin current ≤1.2mA, and SO-8EP package compatibility with industrial PCB layouts.
Technical Context
The AP7362A-18SP-13 integrates a PMOS pass element with internal 0.605V reference, enabling precise 1.8V regulation via factory-trimmed feedback. Its internal compensation eliminates ESR dependency, allowing stable operation with any capacitor type including low-ESR ceramics.
Enable logic operates with VIH ≥1.4V and VIL ≤0.65V, supporting direct connection to 1.8V/3.3V logic. Thermal shutdown activates at TJ = +170°C with +10°C hysteresis, and current limiting clamps peak output to 3.6A during overload.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 1.5A continuous - supports FPGA I/O banks and ASIC core logic without external current boosting |
| Dropout Voltage | 190mV at 1.5A - enables regulation from 2.0V input to 1.8V output, critical for battery-backed systems |
| Output Accuracy | ±1.5% at +25°C - ensures compliance with 1.8V ±2.7% JEDEC tolerance for memory interfaces |
| PSRR | 65dB at 120Hz - suppresses ripple from upstream switching regulators feeding 3.3V/5V rails |
| Quiescent Current | 0.5mA typical - minimizes standby power in always-on network edge devices |
| Thermal Shutdown | +170°C threshold - protects against sustained overloads in enclosed router chassis |
| Package | SO-8EP - exposes thermal pad for 52.8°C/W junction-to-ambient dissipation on 2oz copper PCBs |
Pinout & Package
AP7362A-18SP-13 uses the SO-8EP (exposed pad) package, measuring 4.90mm × 3.85mm × 1.45mm with gull-wing leads and an electrically connected thermal pad recommended for grounding.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Primary ground return path; must be connected to PCB ground plane with low-inductance trace |
| 2 | EN | Active-high enable input; requires ≥1.4V to activate regulator, ≤0.65V to disable |
| 3, 4 | IN | Dual-input pins reduce IR drop and improve high-current stability; both must be routed to input capacitor |
| 5, 6, 7 | OUT | Triple-output pins minimize voltage drop and thermal resistance under 1.5A load |
| 8 | ADJ/NC | No-connect for fixed 1.8V version; left floating or grounded per layout best practice |
Key Features
| Feature | Design Value |
|---|---|
| ESR-independent stability | Operates stably with any capacitor type (ceramic, tantalum, polymer), eliminating ESR tuning effort |
| Low-noise regulation | 100μVrms output noise (100Hz–100kHz) - avoids need for external noise-reduction capacitors in RF-sensitive designs |
| Fast transient response | Load step recovery within 40μs (100mA→1.5A) - maintains voltage integrity during FPGA configuration bursts |
| Robust protection | Integrated current limit (3.6A peak) and thermal shutdown (+170°C) prevent damage during short-circuit or thermal overload |
| Logic-compatible EN | VIH/VIL thresholds compatible with 1.8V and 3.3V GPIO - enables direct microcontroller control without level-shifting |
Applications
| ASIC Power Supplies | FPGA I/O Power |
|---|---|
Use Scenario: Powering ASIC cores in set-top boxes and DVD players where input rail is derived from 3.3V SMPS. IC Role / Device Role / Timing Role: Primary LDO delivering clean 1.8V to ASIC digital logic blocks with fast load-step response. Use Value: 190mV dropout allows operation from degraded 2.0V input during brown-out conditions without reset. | Use Scenario: Supplying configurable I/O banks on Xilinx Artix-7 FPGAs in enterprise routers. IC Role / Device Role / Timing Role: Fixed-output LDO providing regulated 1.8V to LVCMOS18 I/O standards with <100μV noise floor. Use Value: ±1.5% output accuracy ensures setup/hold timing margins meet JEDEC spec across temperature. |
| SMPS Post-Regulation | Industrial Control I/O |
Use Scenario: Filtering ripple from 3.3V buck converter feeding DSP peripherals in graphics cards. IC Role / Device Role / Timing Role: Low-noise post-regulator improving PSRR by 65dB at 120Hz to suppress switching artifacts. Use Value: Eliminates need for additional LC filtering stages, reducing BOM cost and board area. | Use Scenario: Powering isolated digital I/O modules in PLC backplanes operating at −40°C to +85°C. IC Role / Device Role / Timing Role: Industrial-grade LDO with guaranteed operation across full ambient range and thermal shutdown at +170°C. Use Value: SO-8EP package with exposed pad sustains 1.5A load at 85°C ambient using standard 2oz copper thermal relief. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-output LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS7A4700RGWR | 200mA max output, 4μVrms noise, 1.2V to 20V adjustable, SO-8 package | Lower current rating and no fixed 1.8V option - requires external resistor network | Select only if ultra-low noise (<5μV) is prioritized over current capability and simplicity |
| MCP1703T-1802E/MB | 250mA output, 600mV dropout at 250mA, SOT-23-5 package, ±2% accuracy | Insufficient current for FPGA I/O; unsuitable for >500mA loads | Use only in space-constrained, low-power sensor nodes where 1.8V rail draws <200mA |
Compared with TPS7A4700RGWR and MCP1703T-1802E/MB, AP7362A-18SP-13 uniquely delivers 1.5A at 190mV dropout in SO-8EP while maintaining ±1.5% accuracy and ESR-free stability - making it the only viable choice for high-current, thermally demanding 1.8V FPGA/ASIC applications.
Availability
AP7362A-18SP-13 is available at Aetrix Electronics and suitable for FPGA I/O power, ASIC core supplies, and SMPS post-regulation requiring stable component supply across industrial temperature ranges and high-volume production cycles.
Supply support for AP7362A-18SP-13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global semiconductor manufacturer specializing in discrete, analog, and mixed-signal solutions for power management, signal integrity, and connectivity applications.
The AP7362 series belongs to Diodes' high-current LDO portfolio, engineered specifically for powering FPGA, ASIC, and DSP subsystems in networking, computing, and industrial equipment where ultra-low dropout and fast transient response are mandatory.
FAQ
What is the minimum input voltage required for AP7362A-18SP-13 to maintain 1.8V output at 1.5A?
The minimum input voltage is 1.99V, calculated as VOUT + VDROPOUT = 1.8V + 0.19V. The device guarantees regulation down to this level per its 190mV dropout specification at full load and +25°C. At higher temperatures or worst-case process corners, dropout may reach 280mV, requiring VIN ≥ 2.08V for margin.
Can AP7362A-18SP-13 be used with aluminum electrolytic output capacitors?
Yes - the AP7362A-18SP-13's internal compensation architecture ensures stability with any capacitor chemistry, including aluminum electrolytic, tantalum, and ceramic. Unlike traditional LDOs, it imposes no ESR minimum or maximum, eliminating capacitor selection constraints and enabling cost-effective bulk capacitance for hold-up time.
How does the SO-8EP thermal pad affect PCB layout requirements?
The exposed pad (EP) must be soldered to a dedicated copper thermal plane connected to GND. Per Diodes' recommended layout, a 3.3mm × 6.5mm thermal pad with 9 vias (0.35mm diameter) to inner ground layers achieves the specified 52.8°C/W θJA. Using smaller pads or fewer vias degrades thermal performance and risks premature thermal shutdown at 1.5A load.
Is the EN pin internally pulled up or down when not driven?
No - the EN pin has no internal pull-up or pull-down. If unused, it must be externally tied to IN (to force ON) or GND (to force OFF). Leaving EN floating risks indeterminate operation due to noise coupling, potentially causing erratic output enable/disable behavior in noisy industrial environments.
AP7362A-18SP-13 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- *
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- -
- Current - Output:
- 1.5A
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- 1.3 mA
- PSRR:
- 65dB ~ 61dB (120Hz ~ 1kHz)
- Control Features:
- Current Limit, Enable
- Protection Features:
- Over Current, Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO-EP
AP7362A-18SP-13 FAQ
1.How can I place an order for AP7362A-18SP-13 through Aetrix?
Please submit a Request for Quotation (RFQ) for AP7362A-18SP-13 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AP7362A-18SP-13 reliable?
The price and inventory of AP7362A-18SP-13 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AP7362A-18SP-13 is usually 5 days.
3.What payment methods are accepted for AP7362A-18SP-13?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AP7362A-18SP-13 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AP7362A-18SP-13?
AP7362A-18SP-13 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AP7362A-18SP-13 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AP7362A-18SP-13?
For technical support, including AP7362A-18SP-13 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AP7362A-18SP-13 requirements.
6.How does Aetrix verify that AP7362A-18SP-13 is sourced from the original manufacturer or authorized distributors?
All AP7362A-18SP-13 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AP7362A-18SP-13 meets industry standards.
7.What is the process for return or replacement of AP7362A-18SP-13?
All AP7362A-18SP-13 units undergo pre-shipment inspection (PSI). If there is an issue with AP7362A-18SP-13, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AP7362A-18SP-13 part is unused and in its original packaging.
Return procedure for AP7362A-18SP-13:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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