Infineon Technologies BGT60TR13CSWXUMA1

Overview

BGT60TR13CSWXUMA1 from Infineon is a fully integrated 60 GHz FMCW radar transceiver IC with monolithic antenna-in-package (6.5 × 5.0 × 0.9 mm³), three 12-bit RX ADC channels (4 MSps), integrated PLL ramp generator, and on-chip FSM for autonomous frame execution-designed for ultra-low-power gesture sensing behind radomes in consumer electronics.

For engineers reviewing the BGT60TR13CSWXUMA1 datasheet, BGT60TR13CSWXUMA1 pinout, BGT60TR13CSWXUMA1 application, or BGT60TR13CSWXUMA1 equivalent, key selection considerations include its 5.5 GHz RF bandwidth (58–63.5 GHz), dual-domain clocking (80 MHz system / 50 MHz SPI), 196 kbit FIFO buffer, and dedicated VDDLF (3.3 V) supply for PLL loop filter level-shifting.

Technical Context

The device implements a sigma-delta-based 3rd-order RF-PLL with integrated ramp generator to synthesize precise linear FMCW chirps across 58–63.5 GHz, supporting high-resolution range/velocity estimation. Its analog baseband includes per-channel HPF, VGA, and anti-aliasing filters prior to 12-bit differential SAR ADCs.

Digital operation is managed by an embedded finite state machine (FSM) that autonomously sequences radar frames without host intervention after initial trigger-enabling low-duty-cycle operation. Data flow uses a full-duplex 8192 × 24-bit FIFO buffered via standard SPI (≤50 MHz), with dedicated IRQ signaling and hardware reset (DIO3) for deterministic system integration.

Key Specifications

Pinout & Package

Package: 36-ball laminate WLCSP (6.5 × 5.0 × 0.9 mm³), RoHS-compliant, JEDEC J-STD-020 qualified.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 60 GHz FMCW radar frontend applications.

Compared with IWR6843ISK and RW612, BGT60TR13CSWXUMA1 uniquely delivers 60 GHz bandwidth, monolithic AiP, and autonomous FSM in a 6.5 mm × 5.0 mm footprint-making it optimal for space-constrained, low-power gesture interfaces where external RF components and large packages are prohibitive.

Availability

BGT60TR13CSWXUMA1 is available at Aetrix Electronics and suitable for gesture sensing interfaces, smart appliance presence detection, and automotive cabin monitoring requiring stable component supply and qualified automotive-grade packaging.

Supply support for BGT60TR13CSWXUMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, sensors, and automotive ICs, with leadership in radar and RF silicon.

BGT60TR13CSWXUMA1 belongs to Infineon's XENSIV™ 60 GHz radar sensor family, engineered specifically for compact, low-power, antenna-integrated FMCW sensing in consumer and automotive interiors.

FAQ

What reference clock frequency is required for BGT60TR13CSWXUMA1 operation?

The device requires an external 80 MHz clock applied to the OSC_CLK pin (Ball M2). This clock serves as the primary reference for the RF-PLL, MADC, SADC, and FIFO timing domains. It must meet ±50 ppm stability over temperature and supply variations to maintain FMCW chirp linearity and ADC sampling accuracy.

How is radar data transferred from BGT60TR13CSWXUMA1 to the host processor?

Radar IF samples are stored in the on-chip 196 kbit FIFO and read out via standard SPI interface using DI/DO lines. The IRQ pin asserts low upon FIFO fill threshold or frame completion, enabling interrupt-driven burst reads. SPI clock supports up to 50 MHz, allowing full-frame transfer in under 4 ms at maximum rate.

Does BGT60TR13CSWXUMA1 support independent operation without host intervention?

Yes-the integrated finite state machine (FSM) can execute complete radar frames autonomously after initial configuration and trigger. It controls chirp generation, ADC sampling, FIFO write, and power state transitions without host CPU involvement, reducing system-level power consumption during idle periods.

What is the role of the VDDLF pin and why is it supplied at 3.3 V?

VDDLF supplies 3.3 V to the internal level shifter driving the external passive loop filter of the RF-PLL. This higher voltage ensures sufficient drive strength and noise margin for the analog filter components, directly impacting PLL phase noise and FMCW ramp fidelity-critical for sub-centimeter ranging accuracy.