Silicon Labs CP2402-GMR

Overview

CP2402-GMR from Silicon Laboratories is a fixed-function SPI-interface LCD driver with integrated GPIO expander, real-time clock (SmaRTClock), 256-byte SRAM, and dual 16-bit timers. It drives up to 128 segments in 4-mux mode, supports 1.8–3.6 V operation, delivers ultra-low-power LCD mode current of 2.3 µA (typical), and features 5 V-tolerant I/O pins. It is used in battery-powered utility meters and thermostat displays requiring persistent timekeeping and segment control.

For engineers reviewing the CP2402-GMR datasheet, CP2402-GMR pinout, CP2402-GMR application, or CP2402-GMR equivalent, key selection criteria include its 48-pin QFN package, SPI-only interface (no I²C), 128-segment LCD capability, SmaRTClock wake-up alarm, and GPIO port match interrupt functionality - all critical for low-power embedded display systems.

Technical Context

The CP2402-GMR integrates an LCD controller with on-chip charge pump bias generation, supporting static, 2-, 3-, and 4-mux displays without external components. Its SmaRTClock operates from a 32.768 kHz crystal, self-oscillate mode, or external CMOS clock, enabling programmable 36-hour alarms and sub-2.5 µA RTC current.

It uses a 20 MHz internal oscillator for system timing and communicates via 4-wire SPI at up to 2.5 Mbps (synchronous clock) or 1 Mbps (internal clock). All digital I/O pins are 5 V tolerant, and power management includes Ultra Low Power LCD Mode (2.3 µA typ), RAM Preservation Mode (20 µA typ), and Shutdown Mode (0.02 µA typ at 3.0 V).

Key Specifications

Pinout & Package

The CP2402-GMR is housed in a Pb-free 48-pin QFN package (7×7 mm body, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Figure 4.5 in the datasheet Rev. 1.1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LCD driver with RTC applications.

Compared with CP2400-GQ (EOL QFP) and PCF85134TP (I²C-only), the CP2402-GMR offers superior board-space efficiency via QFN packaging, SPI flexibility with synchronous clocking, and unique Port Match wake-up - making it optimal for compact, low-power, interrupt-driven display systems despite its "Not Recommended for New Designs" status.

Availability

CP2402-GMR is available at Aetrix Electronics and suitable for utility metering, programmable thermostats, and home security keypads requiring stable component supply and long-term lifecycle support.

Supply support for CP2402-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in timing, wireless, and mixed-signal ICs for embedded systems.

The CP2400/1/2/3 family was designed as fixed-function display and system auxiliary ICs - integrating LCD driving, RTC, GPIO expansion, and memory to reduce MCU resource load in cost-sensitive, battery-operated consumer and industrial devices.

FAQ

What interface does the CP2402-GMR support?

The CP2402-GMR supports only the 4-wire SPI interface (MOSI, MISO, SCK, NSS) and does not include SMBus or I²C capability. This is confirmed by its block diagram (Figure 1.3), pin definitions (Table 4.1), and ordering information listing CP2402-GM explicitly as an SPI device. Unlike CP2401/CP2403 variants, CP2402-GMR lacks SCL, SDA, SMBA0, and PWR pins - making SPI the sole host communication method for the CP2402-GMR.

Does the CP2402-GMR support 128-segment LCD driving?

Yes, the CP2402-GMR supports up to 128 segments in 4-mux configuration, as stated in the product title ("128/64 SEGMENT LCD DRIVER") and confirmed in Section 1.1 and Figure 1.3. Its pin mapping allocates P0.0–P1.7 (16 pins) as segment drivers and P2.0–P2.3 (4 pins) as COM outputs, enabling full 4-mux operation (16 × 4 = 64 segments per COM bank, total 128). This matches the 48-pin package capability specified for CP2400/CP2402 variants.

What is the package type and footprint of the CP2402-GMR?

The CP2402-GMR uses a Pb-free 48-pin QFN package with a 7×7 mm body and 0.5 mm pitch, as shown in Figure 4.5 (CP2402-GM pinout) and Figure 4.7 (QFN-48 package drawing). The landing pattern follows JEDEC MO-220 VKKD-4, with recommended stencil thickness of 0.125 mm and NSMD pads. This differs from the 48-pin QFP (9×9 mm) used by CP2400-GQ and confirms the "-GM" suffix denotes QFN packaging per Silicon Labs' ordering nomenclature.

Can the CP2402-GMR operate without an external crystal?

Yes, the CP2402-GMR's SmaRTClock supports self-oscillate mode using its internal AGC-controlled oscillator (14 kHz typical), eliminating the need for a 32.768 kHz crystal. This is documented in Section 1 ("SmaRTClock… self-oscillate mode requires no external crystal") and Table 3.4 (ULP SmaRTClock mode current measured in self-oscillate mode). While crystal operation provides higher accuracy, the self-oscillate mode enables crystal-free designs where moderate timekeeping tolerance is acceptable.

Is the CP2402-GMR still recommended for new designs?

No - the CP2402-GMR is marked "Not Recommended for New Designs" on every page of the datasheet (Rev. 1.1), including the cover, block diagrams, and feature summaries. This designation appears alongside EOL notices for CP2402-GM in the Ordering Part Numbers section. While functional and available through Aetrix Electronics for legacy support and existing production, engineers designing new systems should evaluate modern alternatives with active roadmap support and updated power/performance specs.