Cypress Semiconductor Corp CY7C1346H-166AXCT

Overview

CY7C1346H-166AXCT from Cypress Semiconductor is a 2-Mbit (64K × 36) pipelined synchronous SRAM with registered I/O, 3.3V core/3.3V–2.5V I/O operation, 3.5 ns clock-to-output delay at 166 MHz, and JEDEC-standard 100-pin TQFP packaging. It serves as high-speed secondary cache memory in Pentium-class processor systems requiring burst-mode addressing and byte-selectable writes.

For engineers reviewing the CY7C1346H-166AXCT datasheet, CY7C1346H-166AXCT pinout, CY7C1346H-166AXCT application, or CY7C1346H-166AXCT equivalent, key selection criteria include synchronous burst timing compliance, dual-address-strobe (ADSP/ADSC) support, ZZ sleep mode entry/exit latency, and 4-byte write granularity with global write override.

Technical Context

The CY7C1346H-166AXCT implements a two-bit wraparound burst counter fed by A1/A0, supporting both Intel Pentium interleaved and linear burst sequences selected via the MODE strap pin. All synchronous inputs-including address, data, CE1/CE2/CE3, ADSP/ADSC, ADV, BWA–BWD, BWE, and GW-are registered on the rising edge of CLK.

It features asynchronous OE and ZZ controls, synchronous self-timed writes, and common I/O architecture with output registers. The device supports single-cycle ADSC-initiated writes and two-cycle ADSP-initiated writes, with automatic DQ tri-state during write cycles regardless of OE state.

Key Specifications

Pinout & Package

Package: 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch), JEDEC-standard lead-free, RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous burst SRAM applications.

Compared with IS61LV25636A-166TQLI and MT55LSD25636DZ-166:J, the CY7C1346H-166AXCT uniquely combines Pentium-interleaved burst support, asynchronous ZZ sleep, and dual-address-strobe flexibility-making it irreplaceable in legacy x86 cache subsystems where timing and control signal compatibility are non-negotiable.

Availability

CY7C1346H-166AXCT is available at Aetrix Electronics and suitable for Intel Pentium-based industrial controllers, high-speed network packet buffers, real-time DSP data exchange systems, and PCI-X bridge local memory applications requiring stable component supply and long-term obsolescence management.

Supply support for CY7C1346H-166AXCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in high-performance memory, microcontrollers, and programmable analog/digital ICs for industrial, automotive, and communications markets.

The CY7C1346H belongs to Cypress's high-speed synchronous SRAM product line, designed specifically for low-latency, burst-mode cache and buffer applications in x86-compatible and custom high-throughput embedded systems.

FAQ

What is the function of the MODE pin, and how must it be configured?

The MODE pin selects burst address sequence: tied to GND for linear burst, or left floating/VDD for Intel Pentium interleaved burst. It is a static strap pin-must be fixed at power-up and remain unchanged during operation. Internal pull-up ensures default interleaved behavior if unconnected, eliminating need for external biasing in most Pentium designs.

How does the ZZ sleep mode interact with ongoing memory accesses?

Asserting ZZ HIGH places the device in sleep mode after two clock cycles, but pending accesses initiated before ZZ assertion are not guaranteed to complete. The device must be fully deselected (CE1/CE2/CE3 inactive) prior to entering sleep. Recovery requires 2 clock cycles after ZZ returns LOW, and CE1/CE2/CE3 must remain inactive during tZZREC to avoid undefined behavior.

Can ADSP and ADSC be used simultaneously, and what happens if both are asserted?

No-ADSP and ADSC are mutually exclusive. When both are asserted LOW, only ADSP is recognized and ADSC is ignored. This priority ensures deterministic address capture in mixed-processor/controller environments. ADSP is also ignored if CE1 is HIGH, enforcing chip-select gating before strobe evaluation.

What is the timing relationship between ADV and burst address advancement?

ADV must be asserted LOW synchronously with the rising edge of CLK to increment the internal 2-bit burst counter. Each ADV assertion advances to the next address in the selected burst sequence (interleaved or linear). ADV is sampled only during active burst cycles-no effect during single-access or deselected states-and requires no additional setup/hold beyond standard CLK timing.