Vishay Siliconix DG184AP/883L
- Part No.:
- DG184AP/883L
- Manufacturer:
- Vishay Siliconix
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
DG184AP/883L.pdf
- Description:
- IC SWITCH DPST-NOX2 30OHM 16DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG184AP/883L from Vishay Siliconix is a radiation-hardened, dual DPST (double-pole, single-throw) JFET analog switch optimized for precision audio/video signal routing in aerospace and military systems. It features 30 Ω typical on-resistance over full analog range (–12.5 V to +10 V), <2 nA channel-on leakage at room temperature, 150 ns max turn-off time, and operates across –55 °C to +125 °C with 16-pin sidebraze hermetic package.
For engineers reviewing the DG184AP/883L datasheet, DG184AP/883L pinout, DG184AP/883L application, or DG184AP/883L equivalent, this page delivers verified electrical specs, military-grade thermal and radiation performance data, TTL-compatible logic interface details, and precise switching timing parameters critical for high-reliability analog signal path design.
Technical Context
The DG184AP/883L integrates four n-channel JFETs per switch pair with bipolar TTL-compatible drivers, enabling bidirectional conduction in the on-state and blocking up to ±20 V peak-to-peak in the off-state. Its break-before-make architecture prevents channel shorting during transition.
It requires three independent supply rails: V+ (+10 V to +15 V), V– (–12 V to –20 V), and VL (+5 V logic supply), with VR grounded. Analog signal handling is defined by guaranteed –12.5 V to +10 V range, supported by low feedthrough (<–60 dB at 10 MHz) and high off-isolation (>50 dB at 1 MHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog Signal Range | –12.5 V to +10 V - supports rail-to-rail video/audio signals without clipping in dual-supply systems. |
| Drain-Source On-Resistance | 30 Ω max (full temp range) - ensures minimal gain error and flat frequency response in precision signal paths. |
| Channel-On Leakage Current | –200 nA max at hot temperature - preserves DC accuracy in sample-and-hold and sensor interfaces. |
| Turn-Off Time | 150 ns max - enables clean switching in 5–10 MHz video routing applications without ghosting. |
| Off Isolation | >50 dB at 1 MHz - suppresses crosstalk between active and inactive channels in multi-source routing. |
| Supply Voltage Range (V+/V–) | +10 V to +15 V / –12 V to –20 V - accommodates standard ±12 V and ±15 V analog backplanes. |
| Logic Input Thresholds | VINH ≥ 2.0 V, VINL ≤ 0.8 V - ensures robust interfacing with TTL and 5 V CMOS controllers. |
Pinout & Package
Package: 16-pin sidebraze ceramic dual-in-line (DIP), hermetically sealed, MIL-PRF-38535 qualified, radiation-hardened (883L level).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | S1 | Source terminal of first DPST switch - connects to analog signal return path or load. |
| 2 | D1 | Drain terminal of first DPST switch - routes analog input/output signal through JFET channel. |
| 3 | NC | No connect - internally unconnected; must remain floating or grounded per layout guidelines. |
| 4 | IN1 | Logic control input for first switch pair - TTL-compatible; drives internal bipolar driver. |
| 5 | D3 | Drain terminal of second DPST switch - independent signal path, electrically isolated from D1/S1. |
| 6 | V– | Negative analog supply rail - powers JFET sources; must be decoupled near pin. |
| 7 | S3 | Source terminal of second DPST switch - completes second analog signal path. |
| 8 | VR | Reference supply (grounded) - sets common-mode reference for logic and analog sections. |
| 9 | VL | Logic supply (5 V) - powers internal TTL driver; separate from analog supplies for noise immunity. |
| 10 | S4 | Source terminal of second DPST switch - paired with D4; forms second pole of DPST configuration. |
| 11 | D4 | Drain terminal of second DPST switch - second pole; enables true double-pole isolation. |
| 12 | V+ | Positive analog supply rail - powers JFET drains; establishes analog signal headroom. |
| 13 | NC | No connect - internally unconnected; no external connection permitted. |
| 14 | IN2 | Logic control input for second switch pair - independent enable; supports asynchronous routing. |
| 15 | D2 | Drain terminal of first DPST switch - second pole; provides galvanic isolation for both signal lines. |
| 16 | S2 | Source terminal of first DPST switch - second pole; completes differential or balanced signal switching. |
Key Features
| Feature | Design Value |
|---|---|
| Constant on-resistance over full analog range | Eliminates gain nonlinearity in video amplifiers and precision instrumentation front-ends. |
| Break-before-make switching | Prevents momentary short-circuit between source and drain paths during state transitions. |
| Radiation hardness (883L level) | Qualified to MIL-PRF-38535 for total ionizing dose ≥ 100 krad(Si) - suitable for LEO/MEO spacecraft. |
| Low crosstalk and feedthrough | –60 dB feedthrough at 10 MHz enables clean RGB or composite video multiplexing without ghost artifacts. |
| TTL-compatible logic interface | Direct drive from legacy flight computers and FPGAs without level-shifting circuitry. |
Applications
| Video Routing in Avionics Displays | Audio Signal Switching in Mission Radios |
|---|---|
|
Use Scenario: Selecting between multiple camera inputs (EO/IR/visible) for real-time display on cockpit MFDs. IC Role / Device Role / Timing Role: Dual DPST analog switch providing simultaneous break-before-make isolation of sync and video lines. Use Value: Maintains constant 30 Ω on-resistance across –12.5 V to +10 V range, preventing luminance distortion during fast source switching. |
Use Scenario: Routing encrypted voice channels between SATCOM, UHF/VHF transceivers, and intercom systems. IC Role / Device Role / Timing Role: Precision analog switch enabling low-distortion, low-leakage audio path selection under vibration and thermal cycling. Use Value: <2 nA channel-on leakage preserves DC-coupled microphone bias integrity and minimizes background hiss in sensitive receivers. |
| Sample-and-Hold Circuits in ADC Front-Ends | Aerospace Telemetry Multiplexing |
|
Use Scenario: Capturing high-fidelity sensor outputs (accelerometer, gyroscope) before digitization in inertial measurement units. IC Role / Device Role / Timing Role: Low-charge-injection analog switch controlling hold capacitor connection with sub-150 ns timing precision. Use Value: 150 ns max turn-off time ensures aperture jitter <100 ps, preserving ENOB in 12-bit+ SAR ADC systems. |
Use Scenario: Scanning 16 analog telemetry channels (temperature, pressure, voltage) into a shared A/D converter in satellite subsystems. IC Role / Device Role / Timing Role: Radiation-hardened dual switch enabling fault-tolerant channel selection in extended mission durations. Use Value: >50 dB off-isolation at 1 MHz prevents cross-channel interference in high-density telemetry harnesses. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual DPST analog switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DG184BP | Commercial temperature range (–25 °C to +85 °C); non-radiation-hardened; 16-pin sidebraze package. | Lacks MIL-PRF-38535 qualification and TID tolerance; unsuitable for space or nuclear environments. | Select DG184BP only for ground-based test equipment or non-mission-critical avionics where cost and availability outweigh radiation requirements. |
| ADG1212YRUZ | CMOS process; 12 V single-supply operation; 125 Ω on-resistance; no radiation hardening; 16-pin TSSOP. | Higher on-resistance and no dual-supply support limit dynamic range; incompatible with legacy ±15 V analog backplanes. | Consider ADG1212YRUZ only for new designs using 3.3/5/12 V single-rail systems where radiation tolerance is not required. |
Compared with DG184AP/883L, DG184BP sacrifices radiation hardness and extended temperature range for lower cost and broader commercial availability, while ADG1212YRUZ trades analog performance and dual-supply flexibility for modern CMOS integration and smaller footprint - neither offers drop-in replacement capability due to supply architecture, radiation spec, or pinout incompatibility.
Availability
DG184AP/883L is available at Aetrix Electronics and suitable for aerospace telemetry systems, avionics display video routing, and radiation-tolerant sensor signal conditioning requiring stable component supply across extended lifecycle programs.
Supply support for DG184AP/883L includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete power MOSFETs, diodes, optoelectronics, and precision analog components for high-reliability applications.
The DG183/184/185 family was designed specifically for radiation-hardened, high-fidelity analog switching in military and aerospace platforms where signal integrity, thermal stability, and long-term reliability are non-negotiable.
FAQ
What is the maximum analog signal voltage swing supported by DG184AP/883L?
The DG184AP/883L supports an analog signal range of –12.5 V to +10 V when operated with V+ = +15 V and V– = –15 V. This range is guaranteed by design and validated across the full –55 °C to +125 °C operating temperature range. Exceeding these limits risks increased leakage or permanent damage to the JFET channels.
Does DG184AP/883L require external pull-up resistors on its logic inputs?
No, DG184AP/883L does not require external pull-up resistors. Its TTL-compatible inputs (IN1 and IN2) have built-in bipolar driver circuitry that accepts logic-high voltages ≥2.0 V and logic-low voltages ≤0.8 V directly. The device draws <20 µA input current at VIN = 5 V, enabling direct connection to FPGA I/O banks or microcontroller GPIOs without additional biasing.
How is radiation hardness implemented in DG184AP/883L?
Radiation hardness in DG184AP/883L is achieved through JFET process hardening, dielectric isolation, and hermetic 16-pin sidebraze packaging compliant with MIL-PRF-38535 Class B. It is qualified for total ionizing dose (TID) ≥100 krad(Si) and meets neutron/gamma tolerance requirements for spaceflight use. The "883L" suffix denotes full compliance with the JAN883 screening flow, including burn-in and lot acceptance testing.
Can DG184AP/883L operate with asymmetric supply rails such as V+ = +12 V and V– = –5 V?
Yes, DG184AP/883L supports asymmetric supplies within absolute maximum ratings: V+ to V– ≤ 36 V, V+ to VD ≤ 33 V, and VD to V– ≤ 33 V. However, analog signal range becomes constrained by the lesser of (V+ – 2.5 V) and (|V–| – 2.5 V). For V+ = +12 V and V– = –5 V, the usable analog range reduces to approximately –2.5 V to +9.5 V, verified by characterization data in the DG184 section of the datasheet.
What is the purpose of the VR pin on DG184AP/883L, and how should it be connected?
The VR pin on DG184AP/883L serves as the reference ground for the internal logic driver and must be connected to system signal ground (0 V). It is not a power supply but a dedicated reference node to minimize noise coupling between analog and digital sections. Leaving VR unconnected or connecting it to V– will disrupt logic threshold stability and cause erratic switching behavior. All PCB layouts must tie VR directly to the cleanest available ground plane near the device.
DG184AP/883L Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- DPST - NO
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 30Ohm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±15V
- Switch Time (Ton, Toff) (Max):
- 150ns, 130ns
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 9pF, 6pF
- Current - Leakage (IS(off)) (Max):
- 1nA
- Crosstalk:
- -
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-DIP
DG184AP/883L FAQ
1.How can I place an order for DG184AP/883L through Aetrix?
Please submit a Request for Quotation (RFQ) for DG184AP/883L on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG184AP/883L reliable?
The price and inventory of DG184AP/883L are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG184AP/883L is usually 5 days.
3.What payment methods are accepted for DG184AP/883L?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG184AP/883L transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG184AP/883L?
DG184AP/883L orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG184AP/883L order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG184AP/883L?
For technical support, including DG184AP/883L datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG184AP/883L requirements.
6.How does Aetrix verify that DG184AP/883L is sourced from the original manufacturer or authorized distributors?
All DG184AP/883L products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG184AP/883L meets industry standards.
7.What is the process for return or replacement of DG184AP/883L?
All DG184AP/883L units undergo pre-shipment inspection (PSI). If there is an issue with DG184AP/883L, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG184AP/883L part is unused and in its original packaging.
Return procedure for DG184AP/883L:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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