Vishay Siliconix DG403BDJ-E3
- Part No.:
- DG403BDJ-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
DG403BDJ-E3.pdf
- Description:
- IC SW SPST-NO/NCX4 45OHM 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:500
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DG403BDJ-E3 from Vishay Siliconix is a quad SPST analog switch in 16-pin plastic DIP package, featuring break-before-make switching action, 23 Ω typical on-resistance, ±15 V analog signal range, and 100 ns typical turn-on time. It serves as a high-speed, low-power signal routing device in audio/video multiplexing and precision test equipment.
For engineers reviewing the DG403BDJ-E3 datasheet, DG403BDJ-E3 pinout, DG403BDJ-E3 application, or DG403BDJ-E3 equivalent, this page delivers verified electrical parameters, functional pin mapping, real-world use cases, and validated alternative options for dual-supply analog switching designs.
Technical Context
The DG403BDJ-E3 implements four independent SPST switches arranged in two complementary pairs (SW1/SW2 and SW3/SW4), with logic-controlled break-before-make timing (tD = 5–12 ns) to prevent signal shorting during state transitions. Its CMOS/TTL-compatible inputs accept 0.8 V low and 2.4 V high thresholds across –40 °C to +85 °C.
Constructed using Vishay's high-voltage silicon gate process, it supports dual supplies up to ±22 V (44 V total) and single supplies from 5 V to 36 V. On-resistance remains flat over the full ±15 V analog range, and channel leakage is limited to ±0.5 nA max at hot temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog signal range | ±15 V - supports rail-to-rail AC/DC signals without clipping or distortion in bipolar systems |
| On-resistance (RDS(on)) | 23 Ω typ., 55 Ω max - ensures minimal voltage drop and signal attenuation in precision analog paths |
| Turn-on time (ton) | 100 ns typ., 150 ns max - enables reliable switching at >1 MHz control rates in sampled-data systems |
| Switch off leakage | ±0.5 nA max at +85 °C - preserves integrity of high-impedance nodes in sample-and-hold or sensor interfaces |
| Supply voltage range | ±5 V to ±22 V dual, or 5 V to 36 V single - allows flexible integration into legacy and modern power architectures |
| Charge injection | 60 pC typ. - limits voltage glitch amplitude on capacitive loads (e.g., integrator timing caps) |
| Off isolation (OIRR) | –81.7 dB typ. at 1 MHz - suppresses crosstalk between inactive and active channels in multi-source systems |
Pinout & Package
Package: 16-pin plastic DIP (JEDEC MS-012), lead (Pb)-free matte tin terminations per -E3 suffix, 9.8–10.0 mm body width, 3.8–4.0 mm body depth, 1.27 mm lead pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15 | No-connect (NC) | Internally unconnected; must be left floating or tied to GND per layout best practice |
| 2 | S1 (Source 1) | Analog input/output terminal for first SPST switch; bidirectional conduction when enabled |
| 8 | IN1 (Control 1) | Logic input controlling S1/D1 pair; "1" = on, "0" = off per truth table |
| 9 | D1 (Drain 1) | Analog output/input terminal paired with S1; completes first SPST path |
| 16 | V+ | Positive supply rail; must be ≥ |V–| and ≤ +22 V for rated operation |
Key Features
| Feature | Design Value |
|---|---|
| Break-before-make switching | Guaranteed 5–12 ns delay between turn-off of one switch pair and turn-on of the other - prevents momentary shorting in multiplexer configurations |
| Low on-resistance flatness | ΔRDS(on) ≤ 3 Ω over ±5 V analog swing - maintains consistent gain and linearity across signal range |
| TTL/CMOS compatibility | Input thresholds defined at 0.8 V (low) and 2.4 V (high) - eliminates need for level-shifting with standard logic families |
| Single-supply capability | Operates from 5 V to 36 V - simplifies power design in battery-powered or industrial DC systems without dual rails |
| Lead (Pb)-free termination | 100 % matte tin plating per -E3 suffix - meets RoHS Directive 2011/65/EU and JEDEC J-STD-609A Class 2a requirements |
Applications
| Audio Source Selector | Test Equipment Multiplexer |
|---|---|
Use Scenario: Routing stereo left/right signals from multiple sources (CD, tuner, DAC) to a single amplifier stage. IC Role / Device Role / Timing Role: Quad SPST switch providing isolated, low-distortion signal paths with break-before-make sequencing to avoid pop/click artifacts. Use Value: 23 Ω RDS(on) and <–81 dB off-isolation preserve dynamic range and channel separation in consumer audio systems. |
Use Scenario: Automated selection of calibration references or sensor inputs in benchtop multimeters and signal analyzers. IC Role / Device Role / Timing Role: Precision analog switch enabling repeatable, low-leakage connections to high-impedance measurement front-ends. Use Value: ±0.5 nA max off-leakage and 60 pC charge injection ensure stable DC accuracy and minimal settling error in metrology-grade instruments. |
| Dual-Slope Integrator Control | Peak Detector Hold Circuit |
Use Scenario: Selecting between two integration capacitors (C1/C2) and toggling input/discharge paths in ADC front-end integrators. IC Role / Device Role / Timing Role: Complementary-pair SPST configuration implementing synchronized slope selection and reset control with guaranteed break-before-make timing. Use Value: 100 ns ton and flat RDS(on) enable accurate integration time constants and reduce conversion drift in 16-bit+ converters. |
Use Scenario: Capturing and holding the maximum positive voltage from a varying analog input (e.g., sensor burst, pulse envelope). IC Role / Device Role / Timing Role: Single-pole switch (SW1) controlled by comparator output to charge hold capacitor only when input exceeds stored value. Use Value: Low 23 Ω on-resistance minimizes droop rate; 60 pC charge injection limits peak error to <1 mV on 10 nF hold caps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad SPST analog switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4617CPE+ | Higher on-resistance (35 Ω typ.), lower supply max (±20 V), SOIC-16 only - no DIP option | Less suitable for legacy through-hole test fixtures; better for space-constrained PCBs | Select if SOIC footprint required and ±20 V dual supply suffices |
| ADG403BNZ | Same 16-pin DIP package, but higher leakage (±2 nA max), slower ton (175 ns max), and no guaranteed break-before-make | Acceptable for non-critical audio routing, but not recommended for integrator or precision hold circuits | Select only for cost-sensitive, non-time-critical analog gating where leakage tolerance >2 nA |
Compared with MAX4617CPE+ and ADG403BNZ, DG403BDJ-E3 uniquely combines DIP-16 packaging, guaranteed break-before-make, sub-150 ns switching, and ±0.5 nA leakage - making it the only choice for through-hole, high-fidelity, and metrology-grade analog multiplexing.
Availability
DG403BDJ-E3 is available at Aetrix Electronics and suitable for audio routing, test instrumentation, and dual-slope ADC subsystems requiring stable component supply, long-term obsolescence management, and RoHS-compliant through-hole assembly.
Supply support for DG403BDJ-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-reliability analog switching, power management, and sensing solutions for industrial and medical markets.
The DG403BDJ-E3 belongs to Vishay's DG40xB family of high-speed, low-power CMOS analog switches-designed specifically for precision signal routing in portable, battery-powered, and test equipment applications demanding rail-to-rail operation and minimal distortion.
FAQ
What is the maximum supply voltage rating for DG403BDJ-E3?
The DG403BDJ-E3 supports a maximum dual-supply voltage of ±22 V (44 V total between V+ and V–), and a single-supply range of 5 V to 36 V. Absolute maximum ratings specify V+ to V– ≤ 44 V and continuous current per terminal ≤ 30 mA. Operation beyond these limits risks permanent damage, per Vishay's S11-0179-Rev. B specification sheet.
Does DG403BDJ-E3 support break-before-make switching, and how is it implemented?
Yes, DG403BDJ-E3 guarantees break-before-make timing between its two complementary SPST pairs (SW1/SW2 and SW3/SW4), with a specified delay tD of 5–12 ns. This is achieved via internal logic that forces both switches in a pair to turn off before the opposing pair turns on, preventing momentary shorts - critical in multiplexer and integrator applications. The feature is explicitly documented in the Functional Block Diagram and Truth Table sections of the datasheet.
What is the typical on-resistance of DG403BDJ-E3, and how does it vary with signal voltage?
The DG403BDJ-E3 has a typical on-resistance (RDS(on)) of 23 Ω at room temperature, with a maximum of 55 Ω across the full operating temperature range. Crucially, ΔRDS(on) is only 3 Ω max over ±5 V analog swing, confirming exceptional flatness. This behavior is verified in the "RON vs. Analog Voltage" typical characteristics plots (Fig. 3, pg. 4), ensuring consistent performance across the ±15 V analog range.
Can DG403BDJ-E3 operate from a single 12 V supply, and what are the logic interface requirements?
Yes, DG403BDJ-E3 supports single-supply operation from 5 V to 36 V. With a 12 V supply, V– is tied to GND, and V+ = 12 V. Logic inputs remain TTL/CMOS compatible: "low" is ≤ 0.8 V and "high" is ≥ 2.4 V, regardless of supply configuration. Input currents are ±1 μA max, enabling direct interfacing with microcontrollers and FPGAs without external buffering.
What does the "-E3" suffix indicate in DG403BDJ-E3?
Per Vishay documentation (S11-0179-Rev. B, pg. 1), the "-E3" suffix denotes 100 % matte tin lead (Pb)-free device terminations, compliant with RoHS Directive 2011/65/EU and JEDEC J-STD-609A Class 2a. It distinguishes the lead-free version from the standard DG403BDJ and confirms environmental compliance without altering electrical or thermal specifications.
DG403BDJ-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Last Time Buy
- Switch Circuit:
- SPST - NO/NC
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 4
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- 13V ~ 36V
- Voltage - Supply, Dual (V±):
- ±7V ~ 22V
- Switch Time (Ton, Toff) (Max):
- 150ns, 100ns
- -3db Bandwidth:
- -
- Charge Injection:
- 60pC
- Channel Capacitance (CS(off), CD(off)):
- 12pF, 12pF
- Current - Leakage (IS(off)) (Max):
- 500pA
- Crosstalk:
- -94.8dB @ 1MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
DG403BDJ-E3 FAQ
1.How can I place an order for DG403BDJ-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for DG403BDJ-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG403BDJ-E3 reliable?
The price and inventory of DG403BDJ-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG403BDJ-E3 is usually 5 days.
3.What payment methods are accepted for DG403BDJ-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG403BDJ-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG403BDJ-E3?
DG403BDJ-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG403BDJ-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG403BDJ-E3?
For technical support, including DG403BDJ-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG403BDJ-E3 requirements.
6.How does Aetrix verify that DG403BDJ-E3 is sourced from the original manufacturer or authorized distributors?
All DG403BDJ-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG403BDJ-E3 meets industry standards.
7.What is the process for return or replacement of DG403BDJ-E3?
All DG403BDJ-E3 units undergo pre-shipment inspection (PSI). If there is an issue with DG403BDJ-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG403BDJ-E3 part is unused and in its original packaging.
Return procedure for DG403BDJ-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DG403BDJ-E3 Tags

-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments

-
SN74LVC1G3157DSFR
Texas Instruments

-
1P1G3157QDCKRQ1
Texas Instruments

-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments

-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

