Vishay Siliconix DG612DY-T1
- Part No.:
- DG612DY-T1
- Manufacturer:
- Vishay Siliconix
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG612DY-T1.pdf
- Description:
- IC SWITCH SPST-NOX4 45OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG612DY-T1 from Vishay Siliconix is a high-speed, low-glitch quad SPST analog switch IC designed for precision signal routing in fast-switching systems. It features 12 ns turn-on time, 18 Ω on-resistance, ±2 pC charge injection, 500 MHz bandwidth, and operates from ±3 V to ±10.5 V dual supplies or 5–21 V single supply. It is used in pixel-rate video switching and DAC deglitching where minimal transient error and wide analog bandwidth are critical.
For engineers reviewing the DG612DY-T1 datasheet, DG612DY-T1 pinout, DG612DY-T1 application, or DG612DY-T1 equivalent, key selection criteria include guaranteed 12 ns tON at 3 pF load, logic-level compatibility (VIH ≥ 4 V, VIL ≤ 1 V), low RDS(on) matching (ΔRDS(on) ≤ 2 Ω), -40 °C to +85 °C operation, and SOIC-16 package thermal derating (7.6 mW/°C above 75 °C).
Technical Context
The DG612DY-T1 implements four independent SPST switches using Vishay's proprietary D/CMOS process-n-channel DMOS FETs for low RDS(on) and fast switching, paired with low-power CMOS control logic and level translators. Each channel conducts bidirectionally when on and blocks up to 16 Vp-p when off.
Its architecture minimizes parasitic capacitance (CS(on) = 10 pF, CD(off) = 2 pF) and charge injection (Q = 4 pC typ., ΔQ = 3 pC max.) to reduce glitch energy and aperture uncertainty in sample-and-hold and synchronous demodulator circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| tON | 12 ns typical - enables sub-83 MHz switching without timing violation in 3 pF load systems |
| RDS(on) | 18 Ω typical - ensures <0.1 dB insertion loss at 50 Ω system impedance |
| Charge injection | ±2 pC max. - limits step error to <1 LSB in 12-bit 1 nF hold capacitor applications |
| Bandwidth | 500 MHz - supports full-swing NTSC/PAL video and multi-MSPS ADC/DAC interfaces |
| VANALOG range | -5 V to +7 V (V+ = 12 V, V− = −5 V) - accommodates bipolar video and industrial sensor signals |
| Logic thresholds | VIH ≥ 4 V, VIL ≤ 1 V - ensures robust interfacing with 5 V CMOS microcontrollers and FPGAs |
| Off isolation | 74 dB at 5 MHz - suppresses crosstalk between adjacent video or RF channels |
Pinout & Package
Package: 16-pin narrow SOIC (JEDEC MS-012), body dimensions 9.9 mm × 3.9 mm × 1.5 mm, lead pitch 1.27 mm, RoHS-compliant (Pb-free terminations).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 (IN1–IN4) | Digital control inputs | Active-high logic inputs; INx = HIGH turns corresponding switch ON (DG612 logic polarity) |
| 5, 6, 13, 14 (S1–S4) | Source terminals | Analog input nodes; bidirectional conduction path when switch is ON |
| 7, 8, 11, 12 (D1–D4) | Drain terminals | Analog output nodes; connect to load, ADC input, or downstream stage |
| 9 (V−) | Negative supply rail | Bias for NMOS switch FETs; supports dual-supply operation down to −10 V |
| 10 (V+) | Positive supply rail | Bias for PMOS switch FETs; supports up to +21 V single-supply operation |
| 15 (GND) | Ground reference | Logic ground and substrate reference; must be tied to system 0 V |
| 16 (VL) | Logic supply voltage | Separate 4–V+ rail for CMOS control logic; isolates digital noise from analog paths |
Key Features
| Feature | Design Value |
|---|---|
| Fast switching with low glitch energy | 12 ns tON + 8 ns tOFF + ±2 pC charge injection enables clean sampling in >1 MSPS data acquisition |
| Low on-resistance matching | ΔRDS(on) ≤ 2 Ω ensures consistent gain and phase across all four channels in multiplexed video paths |
| Wide analog signal range | Supports ±7 V peak-to-peak signals with V+ = 15 V, V− = −3 V - suitable for industrial sensor front-ends |
| High off-isolation & low crosstalk | 74 dB OIRR and 87 dB XTalk at 5 MHz prevent interference in multi-source video overlay systems |
| Single/dual supply flexibility | Operates from 5–21 V unipolar or ±3–±10.5 V bipolar rails - simplifies power architecture in mixed-signal PCBs |
Applications
| Fast Sample-and-Hold Circuits | Pixel-Rate Video Switching |
|---|---|
Use Scenario: High-speed data acquisition system capturing transient waveforms at >1 MSPS. IC Role / Device Role / Timing Role: DG612DY-T1 acts as the aperture switch, sampling analog input into a hold capacitor with minimal charge kickback. Use Value: 12 ns tON and ±2 pC charge injection limit aperture uncertainty to <12.5 ps and offset error to <0.5 mV in 1 nF hold capacitor designs. | Use Scenario: Overlaying text or graphics onto live composite video in broadcast equipment. IC Role / Device Role / Timing Role: DG612DY-T1 routes background and title video streams under microcontroller control at pixel clock rates (e.g., 13.5 MHz). Use Value: 500 MHz bandwidth preserves luminance/chrominance integrity; 74 dB off-isolation prevents ghosting between sources. |
| DAC Deglitching | Satellite Receiver IF Switching |
Use Scenario: Smoothing staircase output of high-speed DACs before analog filtering. IC Role / Device Role / Timing Role: DG612DY-T1 shorts DAC output to ground during major code transitions to absorb glitch energy. Use Value: Low RDS(on) (18 Ω) and fast tOFF (8 ns) eliminate >90% of 10–100 ns glitches without adding propagation delay. | Use Scenario: Routing L-band IF signals (950–2150 MHz) between multiple LNBs and tuner ICs in satellite set-top boxes. IC Role / Device Role / Timing Role: DG612DY-T1 serves as a low-loss, low-crosstalk analog switch in IF signal path prior to SAW filtering. Use Value: 18 Ω RDS(on) and 2 pF CD(off) maintain <0.3 dB insertion loss and >60 dB port-to-port isolation up to 2 GHz. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4612ESE+ | Higher RDS(on) (35 Ω typ.), slower tON (25 ns), no separate VL pin | Less suitable for <100 ns glitch-critical DAC deglitching; requires shared VCC for logic/analog | Choose when cost sensitivity outweighs speed and isolation requirements |
| ADG1412BRUZ | Lower RDS(on) (1.3 Ω), higher supply voltage limit (+33 V), but larger 16-lead TSSOP package | Better for high-voltage industrial I/O; less optimal for space-constrained video PCBs due to 5 mm × 4.4 mm footprint | Choose when ultra-low on-resistance and extended voltage range are mandatory |
Compared with MAX4612ESE+ and ADG1412BRUZ, the DG612DY-T1 delivers the best balance of speed (12 ns), low charge injection (±2 pC), and compact SOIC-16 packaging for video and high-speed data acquisition-without requiring layout changes or voltage rail redesign.
Availability
DG612DY-T1 is available at Aetrix Electronics and suitable for fast sample-and-hold circuits, pixel-rate video switching, and DAC deglitching requiring stable component supply across industrial, broadcast, and test equipment programs.
Supply support for DG612DY-T1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete components and analog ICs, with leadership in MOSFETs, diodes, optoelectronics, and precision analog switches.
The DG612DY-T1 belongs to Vishay's high-speed D/CMOS analog switch family, engineered specifically for applications demanding minimal switching transients, wide bandwidth, and robust bipolar signal handling in video, instrumentation, and communications systems.
FAQ
What is the maximum analog signal voltage range supported by the DG612DY-T1?
The DG612DY-T1 supports an analog signal range of V− to (V+ − 5 V) under recommended operating conditions. With V+ = 15 V and V− = −3 V, the usable range is −3 V to +10 V. Absolute maximum ratings allow signals from (V− − 0.3 V) to (V+ + 16 V), but sustained operation beyond the recommended range risks increased leakage and distortion. The DG612DY-T1 datasheet specifies VANALOG = −5 V to +7 V at V+ = 12 V, V− = −5 V.
Does the DG612DY-T1 require separate logic and analog supplies?
Yes-the DG612DY-T1 has a dedicated VL pin (Pin 16) for logic supply, independent from V+ and V−. VL must be between 4 V and V+, enabling noise isolation between digital control circuitry and sensitive analog signal paths. This separation reduces digital switching noise coupling into analog channels, a key design advantage over single-rail switches. The DG612DY-T1 achieves this while maintaining full 5 V CMOS logic compatibility.
How does the DG612DY-T1 differ from the DG611DY-T1 in functionality?
The DG612DY-T1 and DG611DY-T1 are functionally identical quad SPST analog switches but with opposite logic polarity: DG612DY-T1 turns switches ON when INx = HIGH (≥4 V), whereas DG611DY-T1 turns them ON when INx = LOW (≤1 V). Both share identical electrical specs-12 ns tON, 18 Ω RDS(on), ±2 pC charge injection-and pinout. The DG612DY-T1 is selected when active-high control aligns with system FPGA or MCU GPIO drive capability.
Can the DG612DY-T1 operate from a single 5 V supply?
No-the DG612DY-T1 requires at minimum two supplies: V+ and V− (dual supply) or V+ and GND with VL referenced to V+ (unipolar). Its internal DMOS architecture needs both positive and negative gate drive voltages to fully enhance complementary FETs. A single 5 V rail cannot bias the NMOS and PMOS switch elements simultaneously. The DG612DY-T1 datasheet specifies unipolar operation only with V+ = 5–21 V, V− = GND, and VL = 4–V+.
What is the thermal derating behavior of the DG612DY-T1 in SOIC-16 package?
The DG612DY-T1 in narrow SOIC-16 package has a power dissipation rating of 600 mW at ≤75 °C ambient. Above 75 °C, it must be derated at 7.6 mW/°C per the datasheet. At 105 °C ambient, maximum allowable power drops to 372 mW. This derating ensures junction temperature remains within safe limits (TJ ≤ 150 °C) under continuous operation. The DG612DY-T1 thermal performance is validated per JEDEC JESD51 standards and applies regardless of supply configuration.
DG612DY-T1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Switch Circuit:
- SPST - NO
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 4
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- 2Ohm
- Voltage - Supply, Single (V+):
- 10V ~ 18V
- Voltage - Supply, Dual (V±):
- ±10V ~ 15V
- Switch Time (Ton, Toff) (Max):
- 35ns, 25ns
- -3db Bandwidth:
- 500MHz
- Charge Injection:
- 4pC
- Channel Capacitance (CS(off), CD(off)):
- 3pF, 2pF
- Current - Leakage (IS(off)) (Max):
- 250pA
- Crosstalk:
- -87dB @ 5MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DG612DY-T1 FAQ
1.How can I place an order for DG612DY-T1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DG612DY-T1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG612DY-T1 reliable?
The price and inventory of DG612DY-T1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG612DY-T1 is usually 5 days.
3.What payment methods are accepted for DG612DY-T1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG612DY-T1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG612DY-T1?
DG612DY-T1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG612DY-T1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG612DY-T1?
For technical support, including DG612DY-T1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG612DY-T1 requirements.
6.How does Aetrix verify that DG612DY-T1 is sourced from the original manufacturer or authorized distributors?
All DG612DY-T1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG612DY-T1 meets industry standards.
7.What is the process for return or replacement of DG612DY-T1?
All DG612DY-T1 units undergo pre-shipment inspection (PSI). If there is an issue with DG612DY-T1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG612DY-T1 part is unused and in its original packaging.
Return procedure for DG612DY-T1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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