Vishay Siliconix DG612DY-T1-E3
- Part No.:
- DG612DY-T1-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG612DY-T1-E3.pdf
- Description:
- IC SWITCH SPST-NOX4 45OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG612DY-T1-E3 from Vishay Siliconix is a high-speed, low-glitch quad SPST analog switch IC designed for precision signal routing in fast-switching systems. It features 12 ns turn-on time, 18 Ω on-resistance, ±2 pC charge injection, 500 MHz bandwidth, and operates from dual supplies (V+ = 5–21 V, V− = −10 to 0 V). It is used in pixel-rate video switching and DAC deglitching where minimal transient error and wide analog bandwidth are critical.
For engineers reviewing the DG612DY-T1-E3 datasheet, DG612DY-T1-E3 pinout, DG612DY-T1-E3 application, or DG612DY-T1-E3 equivalent, key selection criteria include guaranteed low charge injection (±2 pC), logic-level compatibility (VIH ≥ 4 V, VIL ≤ 1 V), SOIC-16 package thermal derating (7.6 mW/°C above 75 °C), and verified performance under bipolar supply conditions (V+ = 15 V, V− = −3 V).
Technical Context
The DG612DY-T1-E3 implements four independent SPST switches using Vishay's proprietary D/CMOS process-integrating n-channel DMOS FETs with low-power CMOS control logic and on-chip level translators. Each switch conducts bidirectionally when on and blocks up to 16 Vp-p when off.
Its architecture minimizes parasitic capacitance (CS(on) = 10 pF, CD(off) = 2 pF) and charge injection (Q = 4 pC typ., ΔQ = 3 pC max.) to suppress glitches in sample-and-hold and synchronous demodulator circuits. The device requires separate logic supply (VL = 4 to V+) and supports unipolar or bipolar analog signal ranges (VANALOG = V− to V+ − 5 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Turn-On Time (tON) | 12 ns typical at RL = 300 Ω, CL = 3 pF - enables sub-20 ns switching for pixel-rate video and fast data acquisition. |
| On-Resistance (RDS(on)) | 18 Ω typical at IS = −1 mA, VD = 0 V - ensures low insertion loss and minimal signal attenuation in 50 Ω systems. |
| Charge Injection (Q) | ±2 pC maximum - limits step-induced offset errors in precision sample-and-hold circuits. |
| Bandwidth | 500 MHz - supports full-spectrum integrity for composite video and RF intermediate-frequency routing. |
| Analog Signal Range | V− to (V+ − 5 V) - allows rail-to-rail analog operation with headroom for internal logic margin under bipolar supplies. |
| Logic Supply (VL) | 4 V to V+ - decouples digital interface voltage from analog supply, enabling mixed-voltage system integration. |
| Off Isolation (OIRR) | 74 dB at 5 MHz - suppresses crosstalk between active and inactive channels in multi-source video switching. |
Pinout & Package
Package: 16-pin narrow-body SOIC (JEDEC MS-012), 3.90 mm width, 1.27 mm pitch, 1.75 mm max height. Thermal derating: 7.6 mW/°C above 75 °C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 (IN1–IN4) | Digital control inputs | Active-high logic; INx = ≥4 V turns corresponding switch ON (DG612 logic polarity per truth table). |
| 5, 6, 13, 14 (S1–S4) | Switch source terminals | Bidirectional analog current paths; each connects to D terminal when switch is ON. |
| 7, 8, 11, 12 (D1–D4) | Switch drain terminals | Bidirectional analog current paths; electrically identical to S pins when switch is ON. |
| 9 (V−) | Negative analog supply | Reference for negative swing; must be ≥ −10 V and ≤ 0.3 V relative to GND. |
| 10 (GND) | Analog ground reference | Common return for V−, VL, and analog signals; separate from digital ground recommended. |
| 15 (V+) | Positive analog supply | Primary analog rail; supports up to +21 V; sets upper limit of analog signal range. |
| 16 (VL) | Logic supply input | Independent 4–V+ supply for CMOS control logic; isolates digital noise from analog path. |
Key Features
| Feature | Design Value |
|---|---|
| Low-glitch architecture | Guaranteed ±2 pC charge injection and 12 ns tON/8 ns tOFF minimize transient energy in fast-settling systems. |
| Bidirectional analog conduction | Each SPST switch conducts equally in both directions when ON, supporting flexible signal path routing without polarity constraints. |
| Wide analog bandwidth | 500 MHz small-signal bandwidth preserves edge fidelity in pixel-clock and IF applications without external equalization. |
| Low quiescent power | 1.2 nW typical supply current enables use in battery-sensitive instrumentation and portable test equipment. |
| Latch-up immunity | Epitaxial isolation layer prevents destructive latch-up under transient overvoltage or ESD stress. |
Applications
| Fast Sample-and-Hold Circuits | Pixel-Rate Video Switching |
|---|---|
|
Use Scenario: High-speed data acquisition system capturing 10+ MSPS analog waveforms with sub-LSB accuracy. IC Role / Device Role / Timing Role: DG612DY-T1-E3 acts as the aperture switch, sampling analog input at precise clock edges with minimal charge kick and droop. Use Value: ±2 pC charge injection and 12 ns tON reduce aperture uncertainty and step error, enabling <12-bit effective resolution at 10 MSPS. |
Use Scenario: Overlay generator inserting text or graphics into live NTSC/PAL video streams in real time. IC Role / Device Role / Timing Role: DG612DY-T1-E3 routes background and title video sources synchronously under pixel-clock timing control. Use Value: 500 MHz bandwidth and 74 dB off-isolation prevent ghosting/halos between sources, preserving composite video integrity. |
| DAC Deglitching | GaAs FET Driver Interface |
|
Use Scenario: Precision waveform synthesizer using R-2R ladder DAC requiring glitch-free output during code transitions. IC Role / Device Role / Timing Role: DG612DY-T1-E3 isolates DAC output during major carry transitions, holding previous value until settling completes. Use Value: Low RDS(on) (18 Ω) and minimal charge injection ensure <10 ns glitch suppression without added RC filtering delay. |
Use Scenario: Phased-array radar front-end requiring rapid GaAs FET bias switching across dozens of RF paths. IC Role / Device Role / Timing Role: DG612DY-T1-E3 delivers precise 0 V or −8 V gate drive to GaAs FETs via complementary SPST outputs. Use Value: Bipolar supply support (V+ = +5 V, V− = −8 V) and 100 mA pulsed current rating enable direct GaAs gate control without level-shifting circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4617ESE+ | Single-supply only (2.7–12 V); 35 ns tON; 60 Ω RDS(on); no V− pin. | Not suitable for bipolar analog rails or sub-20 ns timing-critical paths. | Select when cost-sensitive, single-rail systems require RoHS-compliant TSSOP-16 packaging. |
| ADG1412BRUZ | 44 V max VDD; 13 ns tON; 1.8 Ω RDS(on); requires VSS = GND (no negative supply). | Cannot replicate DG612DY-T1-E3's −10 V to 0 V V− capability or true bidirectional blocking at 16 Vp-p. | Prefer for ultra-low on-resistance in high-precision instrumentation where supply headroom permits GND-referenced VSS. |
Compared with MAX4617ESE+ and ADG1412BRUZ, the DG612DY-T1-E3 uniquely supports true bipolar analog operation (V− down to −10 V), guarantees sub-15 ns switching with <5 pC charge injection, and provides dedicated VL pin for logic/analog supply separation-making it irreplaceable in fast sample-and-hold and sync-locked video overlay designs.
Availability
DG612DY-T1-E3 is available at Aetrix Electronics and suitable for pixel-rate video switching, DAC deglitching, and fast sample-and-hold applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for DG612DY-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete MOSFETs, diodes, optoelectronics, and precision analog switches, with vertical fabrication and rigorous reliability testing.
The DG612DY-T1-E3 belongs to the DG61x family of high-speed D/CMOS analog switches engineered for low-glitch, wide-bandwidth signal routing in test equipment, medical imaging, and broadcast video infrastructure.
FAQ
What is the logic polarity of DG612DY-T1-E3?
The DG612DY-T1-E3 uses active-high logic: an input voltage ≥4 V (VIH) turns the corresponding switch ON, while ≤1 V (VIL) turns it OFF. This is the inverse of DG611, as confirmed by the truth table in Document Number 70057. All four switches in DG612DY-T1-E3 follow this same logic polarity, making it suitable for direct interfacing with standard 5 V CMOS controllers without inverters.
Can DG612DY-T1-E3 operate from a single 5 V supply?
Yes, DG612DY-T1-E3 supports unipolar operation: V+ = 5 V, V− = GND (0 V), VL = 5 V, and analog signals from 0 V to 0 V (i.e., ground-referenced). However, its specified analog signal range becomes 0 V to (V+ − 5 V) = 0 V, so full-range unipolar use requires V+ ≥ 10 V. For true 0–5 V analog switching, configure V+ = 12 V, V− = 0 V, VL = 5 V per the Recommended Operating Range table.
What is the maximum allowable analog signal voltage swing for DG612DY-T1-E3?
The DG612DY-T1-E3 guarantees blocking of up to 16 Vp-p when OFF, with absolute maximum ratings allowing VS or VD from (V− − 0.3 V) to (V+ + 16 V). Under recommended operation (V+ = 15 V, V− = −3 V), the usable analog range is V− to (V+ − 5 V), i.e., −3 V to +10 V. Exceeding these limits risks clamping by internal diodes or permanent damage per Absolute Maximum Ratings.
Does DG612DY-T1-E3 require external bypass capacitors?
Yes, stable operation requires local 0.1 µF ceramic bypass capacitors between V+ and GND, V− and GND, and VL and GND, placed within 5 mm of the respective pins. This is mandated by the "Notes" section (page 3) to suppress supply transients that could induce false switching or degrade charge injection performance-especially critical in high-speed sample-and-hold and video applications.
Is DG612DY-T1-E3 RoHS compliant?
Yes, DG612DY-T1-E3 is RoHS compliant. The "-E3" suffix denotes lead (Pb)-free terminations per JEDEC J-STD-609. While the datasheet notes "Pb containing terminations are not RoHS compliant," the "-E3" variant explicitly meets RoHS Directive 2011/65/EU and is shipped with matte-tin plating. Full compliance documentation is available via Vishay's PPAP portal under part number DG612DY-T1-E3.
DG612DY-T1-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Switch Circuit:
- SPST - NO
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 4
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- 2Ohm
- Voltage - Supply, Single (V+):
- 10V ~ 18V
- Voltage - Supply, Dual (V±):
- ±10V ~ 15V
- Switch Time (Ton, Toff) (Max):
- 35ns, 25ns
- -3db Bandwidth:
- 500MHz
- Charge Injection:
- 4pC
- Channel Capacitance (CS(off), CD(off)):
- 3pF, 2pF
- Current - Leakage (IS(off)) (Max):
- 250pA
- Crosstalk:
- -87dB @ 5MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DG612DY-T1-E3 FAQ
1.How can I place an order for DG612DY-T1-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for DG612DY-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG612DY-T1-E3 reliable?
The price and inventory of DG612DY-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG612DY-T1-E3 is usually 5 days.
3.What payment methods are accepted for DG612DY-T1-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG612DY-T1-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG612DY-T1-E3?
DG612DY-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG612DY-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG612DY-T1-E3?
For technical support, including DG612DY-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG612DY-T1-E3 requirements.
6.How does Aetrix verify that DG612DY-T1-E3 is sourced from the original manufacturer or authorized distributors?
All DG612DY-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG612DY-T1-E3 meets industry standards.
7.What is the process for return or replacement of DG612DY-T1-E3?
All DG612DY-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with DG612DY-T1-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG612DY-T1-E3 part is unused and in its original packaging.
Return procedure for DG612DY-T1-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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