Vishay Siliconix DG613AEY-T1-E3
- Part No.:
- DG613AEY-T1-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG613AEY-T1-E3.pdf
- Description:
- IC SW SPST-NO/NCX4 115OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG613AEY-T1-E3 from Vishay Siliconix is a quad SPST analog switch IC with mixed configuration (2 normally open, 2 normally closed), designed for precision signal routing in high-speed, low-distortion systems. It delivers 1 pC typical charge injection, 720 MHz 3 dB bandwidth, and rail-to-rail analog signal handling across ±5 V or +3 V/+5 V single supplies - enabling use in medical instrumentation front-ends and automated test equipment multiplexing stages.
For engineers reviewing the DG613AEY-T1-E3 datasheet, DG613AEY-T1-E3 pinout, DG613AEY-T1-E3 application, or DG613AEY-T1-E3 equivalent, key selection criteria include its break-before-make timing (15 ns at ±5 V), leakage < 0.25 nA at 85 °C, and guaranteed 2 V logic-high compatibility with +5 V/±5 V supplies - critical for low-error data acquisition channel switching.
Technical Context
The DG613AEY-T1-E3 implements four independent CMOS transmission gates with complementary control logic: SW1/SW4 activate on logic high, SW2/SW3 on logic low - enabling simultaneous NO/NC switching without external inversion. Its RON of 115 Ω max (±5 V) and flatness of 40 Ω (±5 V) ensure minimal gain error across full analog range (–5 V to +5 V).
Charge injection (1 pC typ.) and off-isolation (–62 dB at 10 MHz) are tightly controlled via matched transistor geometry and guard-ring layout. The device operates across –40 °C to +125 °C and supports dual-supply (±2.7 V to ±5 V) or single-supply (2.7 V to 12 V) biasing - with all specifications fully characterized at +3 V, +5 V, and ±5 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Configuration | 2 × NO + 2 × NC SPST - enables simultaneous signal path selection and redundancy in safety-critical routing |
| Charge Injection | 1 pC typical - minimizes voltage glitch in sample-and-hold and precision ADC input stages |
| 3 dB Bandwidth | 720 MHz - supports high-speed serial data switching up to 100 Mbps without signal degradation |
| On-Resistance (RON) | 115 Ω maximum at ±5 V - ensures < 0.1% gain error in 50 Ω/600 Ω impedance-matched circuits |
| Off-Isolation | –62 dB at 10 MHz - suppresses crosstalk between adjacent channels in dense multichannel DAQ systems |
| Supply Range | ±2.7 V to ±5 V dual or +2.7 V to +12 V single - compatible with legacy ±5 V and modern low-voltage 3.3 V systems |
| Logic Threshold | 2 V high / 0.8 V low at +5 V - interfaces directly with 3.3 V and 5 V CMOS/TTL without level-shifting |
Pinout & Package
Package: 16-pin narrow SOIC (JEDEC MS-012), 10.0 mm × 4.0 mm × 1.75 mm body height, RoHS-compliant, halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1–IN4 | Digital control inputs | CMOS/TTL-compatible logic signals controlling individual switches; IN1/IN4 enable SW1/SW4 (NO), IN2/IN3 enable SW2/SW3 (NC) |
| S1–S4 | Switch source terminals | Analog inputs for each SPST channel; bidirectional conduction supports signal routing in either direction |
| D1–D4 | Switch drain terminals | Analog outputs; paired with S1–S4 to form four independent transmission paths |
| V+ | Positive supply rail | Accepts +2.7 V to +12 V (single) or +5 V (dual); powers internal logic and switch driver circuitry |
| V− | Negative supply rail | Accepts –2.7 V to –5 V (dual only); enables true bipolar analog signal handling (–5 V to +5 V) |
| GND | Ground reference | System ground return for digital logic and substrate bias; must be low-impedance for noise immunity |
| NC | No-connect terminal | Internally unconnected; must remain floating or tied to GND per layout guidelines to avoid parasitic coupling |
Key Features
| Feature | Design Value |
|---|---|
| Mixed NO/NC configuration | Enables fail-safe signal path selection - e.g., default connection maintained during control loss in medical sensor interfaces |
| Rail-to-rail analog range | Supports full-swing signals from V− to V+ (e.g., –5 V to +5 V), eliminating clipping in wide-dynamic-range instrumentation |
| Break-before-make timing | 15 ns delay (±5 V) prevents momentary shorting between channels during state transitions - critical for power-sensitive analog muxes |
| Low temperature drift | RON flatness ≤ 55 Ω over –40 °C to +125 °C ensures stable channel matching in automotive under-hood applications |
| Miniature packaging | 16-pin narrow SOIC footprint (10.0 × 4.0 mm) allows high-density placement in portable test equipment PCBs |
Applications
| Medical Instrumentation | Precision Data Acquisition |
|---|---|
Use Scenario: Multiplexing ECG electrode inputs into a single high-resolution ADC channel while maintaining baseline stability. IC Role / Device Role / Timing Role: Quad SPST switch routes four differential biopotential signals with sub-pC charge injection to prevent baseline wander. Use Value: 1 pC charge injection and –62 dB off-isolation eliminate cross-channel interference, preserving microvolt-level signal integrity. |
Use Scenario: Channel selection in 18-bit automated test equipment (ATE) systems requiring < 0.01% gain error and low THD. IC Role / Device Role / Timing Role: Low-RON (115 Ω max) and flat RON (40 Ω) minimize channel-to-channel gain mismatch during sequential sampling. Use Value: 720 MHz bandwidth and 0.01% THD support accurate digitization of fast transients up to 10 MHz without aliasing. |
| High-Speed Communications | Sample-and-Hold Systems |
Use Scenario: Signal path switching in RF test set front-ends where multiple signal sources feed a common spectrum analyzer input. IC Role / Device Role / Timing Role: High isolation (–62 dB) and low crosstalk (–90 dB) prevent leakage between LTE, 5G, and Wi-Fi test signals. Use Value: 16 ns tOFF enables rapid reconfiguration between frequency bands without interrupting measurement continuity. |
Use Scenario: Hold capacitor charging in precision sample-and-hold amplifiers used in high-speed oscilloscope vertical sections. IC Role / Device Role / Timing Role: Ultra-low charge injection (1 pC) minimizes voltage step on hold capacitor during acquisition-to-hold transition. Use Value: Ensures < 1 LSB error in 16-bit systems even after 100 kS/s sampling, extending effective resolution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad SPST analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4613ESE+ | Higher RON (180 Ω max), lower bandwidth (300 MHz), no BBM timing spec | Less suitable for >50 Mbps high-speed routing; acceptable for DC-coupled industrial I/O modules | Prefer DG613AEY-T1-E3 when bandwidth >500 MHz or charge injection <2 pC is required |
| ADG1412BRUZ | Lower RON (1.8 Ω typ.), but higher charge injection (12 pC), 400 MHz bandwidth | Better for low-impedance power-switching; unsuitable for precision sample-and-hold due to charge error | Select DG613AEY-T1-E3 for sub-pC charge injection and >700 MHz bandwidth in signal-chain front-ends |
Compared with MAX4613ESE+ and ADG1412BRUZ, DG613AEY-T1-E3 uniquely balances ultra-low charge injection (1 pC), high bandwidth (720 MHz), and mixed NO/NC topology - making it optimal for medical-grade multiplexing and high-fidelity ATE where signal fidelity outweighs absolute RON minimization.
Availability
DG613AEY-T1-E3 is available at Aetrix Electronics and suitable for medical instrumentation, automated test equipment, and high-end data acquisition systems requiring stable component supply across extended temperature ranges (–40 °C to +125 °C).
Supply support for DG613AEY-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-reliability analog switching, power MOSFETs, and precision resistors.
The DG613AEY-T1-E3 belongs to Vishay's DG61xA family of precision analog switches, engineered for low distortion, low leakage, and robust operation in demanding instrumentation and test environments.
FAQ
What is the maximum supply voltage rating for DG613AEY-T1-E3?
The DG613AEY-T1-E3 has an absolute maximum V+ to V− rating of 14 V. When operated from dual supplies, it supports ±2.7 V to ±5 V; for single-supply use, it accepts +2.7 V to +12 V. Exceeding these limits risks permanent damage, as specified in the Absolute Maximum Ratings table of the DG613AEY-T1-E3 datasheet.
Does DG613AEY-T1-E3 support rail-to-rail analog signal switching?
Yes, DG613AEY-T1-E3 supports true rail-to-rail analog signal handling: –5 V to +5 V with ±5 V supplies, and 0 V to +3 V or 0 V to +5 V with single-ended supplies. This capability is enabled by its fully enhanced CMOS process and verified across all operating temperatures (–40 °C to +125 °C) per DG613AEY-T1-E3 specifications.
What is the logic configuration for the four switches in DG613AEY-T1-E3?
DG613AEY-T1-E3 features a mixed configuration: SW1 and SW4 are normally open (activate on logic high), while SW2 and SW3 are normally closed (deactivate on logic high). This is confirmed in the Truth Table on page 2 of the DG613AEY-T1-E3 datasheet and enables flexible signal path redundancy and default-state safety in critical systems.
How does DG613AEY-T1-E3 achieve 1 pC typical charge injection?
DG613AEY-T1-E3 achieves 1 pC typical charge injection through matched transistor sizing, optimized gate overlap reduction, and integrated charge cancellation structures in its silicon layout. This value is measured at Vg = 0 V, Rg = 0 Ω, CL = 1 nF per the DG613AEY-T1-E3 test circuit (Figure 3), and is validated across –40 °C to +125 °C.
Is DG613AEY-T1-E3 pin-compatible with earlier DG613 variants?
Yes, DG613AEY-T1-E3 is pin-compatible with other DG613A variants in the same package - including DG613AEQ-T1-E3 (TSSOP) and DG613AEN-T1-E4 (miniQFN). All share identical pin numbering, function mapping, and SOIC footprint per the DG613A Functional Block Diagram and Pin Configuration diagrams in the DG613AEY-T1-E3 datasheet.
DG613AEY-T1-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Switch Circuit:
- SPST - NO/NC
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 4
- On-State Resistance (Max):
- 115Ohm
- Channel-to-Channel Matching (ΔRon):
- 700mOhm
- Voltage - Supply, Single (V+):
- 2.7V ~ 12V
- Voltage - Supply, Dual (V±):
- ±2.7V ~ 5V
- Switch Time (Ton, Toff) (Max):
- 55ns, 35ns
- -3db Bandwidth:
- 720MHz
- Charge Injection:
- 1pC
- Channel Capacitance (CS(off), CD(off)):
- 2pF, 3pF
- Current - Leakage (IS(off)) (Max):
- 100pA
- Crosstalk:
- -90dB @ 10MHz
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DG613AEY-T1-E3 FAQ
1.How can I place an order for DG613AEY-T1-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for DG613AEY-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG613AEY-T1-E3 reliable?
The price and inventory of DG613AEY-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG613AEY-T1-E3 is usually 5 days.
3.What payment methods are accepted for DG613AEY-T1-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG613AEY-T1-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG613AEY-T1-E3?
DG613AEY-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG613AEY-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG613AEY-T1-E3?
For technical support, including DG613AEY-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG613AEY-T1-E3 requirements.
6.How does Aetrix verify that DG613AEY-T1-E3 is sourced from the original manufacturer or authorized distributors?
All DG613AEY-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG613AEY-T1-E3 meets industry standards.
7.What is the process for return or replacement of DG613AEY-T1-E3?
All DG613AEY-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with DG613AEY-T1-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG613AEY-T1-E3 part is unused and in its original packaging.
Return procedure for DG613AEY-T1-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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