Vishay Siliconix DG613DY-E3

Overview

DG613DY-E3 from Vishay Siliconix is a high-speed, low-glitch quad analog switch IC with two normally open (NO) and two normally closed (NC) SPST switches configurable as four SPST, two SPDT, or one DPDT. It delivers 12 ns turn-on time, 18 Ω R_DS(on), ±2 pC charge injection, and 500 MHz bandwidth for precision video and sample-and-hold systems.

For engineers reviewing the DG613DY-E3 datasheet, DG613DY-E3 pinout, DG613DY-E3 application, or DG613DY-E3 equivalent, key selection criteria include its dual logic-controlled NO/NC topology, bipolar analog signal range (V− to V+ − 5 V), 5 V CMOS-compatible control inputs, and SOIC-16 package compatibility with high-density PCB layouts.

Technical Context

The DG613DY-E3 uses Vishay's proprietary D/CMOS process integrating n-channel DMOS switching FETs with low-power CMOS drivers and level translators, enabling fast bidirectional conduction and latchup immunity via epitaxial isolation. Its internal architecture supports independent control of SW1/SW4 (active-high) and SW2/SW3 (active-low) with logic thresholds at ≤1 V (low) and ≥4 V (high).

It operates from dual supplies (V+ = 5–21 V, V− = −10 to 0 V) or unipolar configurations, with analog signal handling up to ±16 V_p-p when off and guaranteed R_DS(on) matching (<2 Ω) across channels - critical for balanced video switching and synchronous demodulation paths.

Key Specifications

Pinout & Package

Package: 16-pin narrow SOIC (JEDEC MS-012), 3.9 × 9.9 mm footprint, 1.27 mm pitch, RoHS-compliant (E3 suffix).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog switch applications.

Compared with MAX4613ESA+ and ADG1414BRUZ, the DG613DY-E3 uniquely integrates two NO and two NC switches in one SOIC-16 package, enabling native DPDT operation without external components - reducing BOM count and layout complexity in video routing and RF driver designs.

Availability

DG613DY-E3 is available at Aetrix Electronics and suitable for high-speed video routing, precision sample-and-hold systems, and GaAs FET driver circuits requiring stable component supply, long-term manufacturability, and RoHS-compliant packaging.

Supply support for DG613DY-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Vishay Siliconix is a global semiconductor manufacturer specializing in discrete MOSFETs, diodes, optoelectronics, and precision analog switches - known for high-reliability, high-speed silicon processes.

The DG613DY-E3 belongs to Vishay's D/CMOS analog switch family, engineered for applications demanding nanosecond switching, ultra-low glitch, and robust bipolar signal handling - especially in broadcast video, test equipment, and defense RF subsystems.

FAQ

What is the maximum analog signal voltage range supported by the DG613DY-E3?

The DG613DY-E3 supports an analog signal range from V− to (V+ − 5) V. With recommended operating voltages of V+ = 5–21 V and V− = −10 to 0 V, this yields a usable range up to ±16 V_p-p when properly biased. Absolute maximum ratings allow V+ to V− up to 21 V, but sustained operation beyond the recommended range risks increased leakage and reduced reliability. The DG613DY-E3 internal clamp diodes protect against transient overvoltage, provided forward current remains within 20 mA limits.

How does the DG613DY-E3 achieve low charge injection, and why is it critical?

The DG613DY-E3 achieves ±2 pC typical charge injection through optimized DMOS gate geometry and matched parasitic capacitances in Vishay's proprietary D/CMOS process. This low value is critical in sample-and-hold and switched-capacitor filter applications because injected charge causes step errors at the hold capacitor, directly degrading DC accuracy and settling time. In a 1 nF hold capacitor, ±2 pC translates to just ±2 mV offset - enabling sub-12-bit error performance without trimming. The DG613DY-E3's guaranteed ΔQ ≤4 pC across ±3 V analog swing further ensures consistent behavior across signal amplitudes.

Can the DG613DY-E3 be used with a single 5 V supply, and what are the trade-offs?

Yes, the DG613DY-E3 can operate from a single 5 V supply (V+ = 5 V, V− = GND, VL = 5 V), supporting unipolar analog signals from 0 V to 2 V (since V_ANALOG = V− to V+ − 5 = 0 to 0 V - invalid). Per specifications, unipolar mode requires V+ ≥ 10 V to yield usable range; thus, true single-supply use demands V+ = 12 V or higher with V− = 0 V, giving 0–7 V analog swing. Trade-offs include reduced dynamic range versus dual-supply operation and higher R_DS(on) (25 Ω typical at V+ = 12 V, V− = 0 V vs. 18 Ω at V+ = 15 V, V− = −3 V). The DG613DY-E3 truth table and logic thresholds remain unchanged.

What is the thermal derating behavior of the DG613DY-E3 in SOIC-16 package?

The DG613DY-E3 in narrow SOIC-16 has a power dissipation rating of 600 mW at ≤75 °C ambient. Above 75 °C, it must be derated at 7.6 mW/°C per the datasheet - meaning at 105 °C ambient, maximum allowable power drops to 600 mW − (30 °C × 7.6 mW/°C) = 372 mW. This derating applies to total package power (I+ × V+ + I− × |V−| + I_L × V_L). Junction temperature must stay below 150 °C; with θ_JA ≈ 125 °C/W for SOIC-16, 372 mW yields ~46 °C rise - keeping T_J at 151 °C marginally exceeds limit, so forced airflow or copper pour is advised above 85 °C. The DG613DY-E3 thermal design must account for simultaneous switching of all four channels.

Does the DG613DY-E3 require external bypass capacitors, and where should they be placed?

Yes, the DG613DY-E3 requires local bypassing: a 0.1 µF ceramic capacitor between VL and GND, and separate 1 µF tantalum or ceramic caps between V+ and GND and V− and GND. These must be placed within 5 mm of their respective pins to suppress high-frequency switching noise and prevent logic glitches caused by supply bounce. Poor bypassing increases charge injection variance and degrades off-isolation (OIRR drops >10 dB at 5 MHz if VL decoupling is omitted). For optimal video performance, a second 10 nF cap in parallel with the 0.1 µF VL bypass further stabilizes the logic threshold. The DG613DY-E3 layout guidelines specify separate analog and digital ground traces converging at a single point near the GND pin.