Vishay Siliconix DG613DY-T1
- Part No.:
- DG613DY-T1
- Manufacturer:
- Vishay Siliconix
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG613DY-T1.pdf
- Description:
- IC SWITCH SPST X 4 45OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG613DY-T1 from Vishay Siliconix is a high-speed, low-glitch quad analog switch IC with two normally open (NO) and two normally closed (NC) SPST switches in a 16-pin narrow SOIC package. It features 12 ns turn-on time, 18 Ω RDS(on), ±2 pC charge injection, 500 MHz bandwidth, and operates from ±5 V to ±10.5 V dual supplies or 5–21 V single supply. It is used in pixel-rate video switching and DAC deglitching where fast, clean signal routing is critical.
For engineers reviewing the DG613DY-T1 datasheet, DG613DY-T1 pinout, DG613DY-T1 application, or DG613DY-T1 equivalent, key selection criteria include verified SPDT/DPDT reconfigurability, guaranteed 12 ns tON at 3 pF load, low 2 pC charge injection for sample-and-hold accuracy, and compatibility with 5 V CMOS logic control levels (VIL ≤ 1 V, VIH ≥ 4 V).
Technical Context
The DG613DY-T1 implements four independent lateral DMOS analog switches fabricated on Vishay's proprietary D/CMOS process, integrating n-channel DMOS FETs with low-power CMOS drivers and level translators. Each switch conducts bidirectionally when ON and blocks up to 16 Vp-p when OFF, with minimized parasitic capacitances (CS(on) = 10 pF, CD(off) = 2 pF) to ensure fast settling and low glitch energy.
Its logic interface accepts 5 V CMOS-compatible inputs (VIL ≤ 1 V, VIH ≥ 4 V), referenced to VL pin, while analog signal range spans V– to (V+ – 5) V under recommended operation. The device includes an epitaxial layer to prevent latch-up and supports unipolar or bipolar supply configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| tON | 12 ns - Enables sub-83 MHz switching without aperture uncertainty in sampling systems |
| RDS(on) | 18 Ω typical - Ensures low insertion loss (<0.1 dB at 100 kHz) and minimal signal distortion |
| Charge injection | ±2 pC - Limits step error to <2 mV on 1 nF hold capacitor, critical for precision sample-and-hold |
| Bandwidth | 500 MHz - Supports full-swing video signals up to 1080p60 without attenuation |
| OIRR | 74 dB at 5 MHz - Provides strong isolation between active and inactive channels in multi-source routing |
| VANALOG range | V– to (V+ – 5) V - Allows rail-to-rail analog signal handling with headroom for internal logic margin |
| Supply voltage | V+ = 5–21 V, V– = –10–0 V - Supports flexible dual-supply operation for ±5 V, ±10 V, or +12 V/–3 V systems |
Pinout & Package
Package: 16-pin narrow SOIC (JEDEC MS-012), body dimensions 9.9 mm × 3.9 mm × 1.5 mm, 1.27 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3, IN4 | Digital control inputs | Accept 5 V CMOS logic; IN1/IN4 control SW1/SW4 (NO), IN2/IN3 control SW2/SW3 (NC) |
| S1–S4 | Switch source terminals | Bidirectional analog current paths; each connects to corresponding Dx when switch is ON |
| D1–D4 | Switch drain terminals | Analog I/O nodes; paired with Sx to form four independent SPST switches |
| V+, V– | Analog supply rails | Set analog signal range; must be within absolute max (–0.3 V to 21 V) and derated above 75 °C |
| GND | Logic ground reference | Return path for digital control circuitry; separate from analog ground to minimize noise coupling |
| VL | Logic supply reference | Defines logic threshold (VIL/VIH); tied to 5 V for standard CMOS compatibility |
Key Features
| Feature | Design Value |
|---|---|
| Configurable switch topology | Two NO + two NC SPST switches enable hardware-selectable 4×SPST, 2×SPDT, or 1×DPDT routing without external components |
| Low-glitch architecture | Minimized charge injection (±2 pC) and fast tON/tOFF (12 ns/8 ns) reduce transient artifacts in video and sampled-data systems |
| Bidirectional conduction | Identical RDS(on) and leakage in both directions ensures signal integrity regardless of source/sink orientation |
| Latch-up immunity | Epitaxial substrate prevents destructive latch-up under overvoltage or ESD stress per JEDEC JESD78 |
| Wide supply flexibility | Operates from single 5–21 V or dual ±5 V to ±10.5 V supplies, simplifying power domain integration |
Applications
| Fast Sample-and-Hold Circuits | Pixel-Rate Video Switching |
|---|---|
Use Scenario: High-speed data acquisition system capturing 10+ MSPS analog waveforms with sub-LSB accuracy. IC Role / Device Role / Timing Role: DG613DY-T1 acts as the aperture switch, sampling input during precise clock-controlled ON window with minimal charge kickback. Use Value: ±2 pC charge injection limits hold-step error to <2 mV on 1 nF capacitor, enabling 12-bit effective resolution without trimming. | Use Scenario: Overlay generator inserting text or graphics into composite video stream at 13.5 MHz pixel clock rate. IC Role / Device Role / Timing Role: DG613DY-T1 routes background and title video sources using synchronized 5 V logic, configured as two SPDTs. Use Value: 500 MHz bandwidth preserves rise/fall times <2.5 ns, eliminating halos and edge smearing in overlay transitions. |
| DAC Deglitching | GaAs FET RF Switch Drivers |
Use Scenario: Precision DAC output stage removing switching transients before feeding to low-pass reconstruction filter. IC Role / Device Role / Timing Role: DG613DY-T1 isolates DAC output during code transitions, then reconnects after settling completes. Use Value: 12 ns tON and low RDS(on) (18 Ω) minimize glitch duration and amplitude, reducing post-filter ripple by >20 dB. | Use Scenario: Phased array radar front-end requiring fast, low-power bias switching for GaAs FET transmit/receive paths. IC Role / Device Role / Timing Role: DG613DY-T1 provides complementary gate drive: S1 applies 0 V (ON), S2 applies –8 V (OFF) to same FET. Use Value: Bidirectional blocking to ±16 Vp-p and 100 mA pulsed current rating support reliable RF switch control without external level shifters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4617ESE+ | Single-supply only (2.7–12 V), 100 Ω RDS(on), 25 ns tON, no NC/NO configuration | Limited to unipolar systems; unsuitable for ±10 V video or bipolar DAC interfaces | Select when cost-sensitive, low-frequency (<1 MHz) switching suffices and dual supply is unavailable |
| ADG1412BRUZ | 4-channel SPST, 1.5 Ω RDS(on), 100 ns tON, no NC/NO, requires external logic for SPDT emulation | Superior on-resistance but slower switching; lacks native DPDT reconfiguration | Prefer for ultra-low distortion audio or precision instrumentation where speed is secondary to linearity |
Compared with MAX4617ESE+ and ADG1412BRUZ, the DG613DY-T1 uniquely combines configurable NO/NC topology, 12 ns speed, and ±16 Vp-p blocking in a single SOIC package-enabling compact, high-fidelity video and RF switch designs without layout compromises.
Availability
DG613DY-T1 is available at Aetrix Electronics and suitable for fast sample-and-hold circuits, pixel-rate video switching, and DAC deglitching requiring stable component supply across industrial, broadcast, and test equipment programs.
Supply support for DG613DY-T1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete MOSFETs, diodes, optoelectronics, and precision analog switches, with vertical fabrication and rigorous reliability testing.
The DG613DY-T1 belongs to Vishay's high-speed D/CMOS analog switch family, engineered for applications demanding nanosecond switching, low charge injection, and robust bipolar supply operation in video, instrumentation, and communications systems.
FAQ
What is the maximum analog signal voltage range supported by the DG613DY-T1?
The DG613DY-T1 supports an analog signal range from V– to (V+ – 5) V under recommended operating conditions. With V+ = 15 V and V– = –3 V, this yields –3 V to +10 V. Absolute maximum ratings allow VS/VD up to (V+ + 16) V or (V– – 0.3) V, but sustained operation beyond the recommended range risks increased leakage or distortion. Always verify signal swing against actual supply rails in the DG613DY-T1 design.
Can the DG613DY-T1 be used with a single 5 V supply?
Yes, the DG613DY-T1 operates with a single 5 V supply (V+ = 5 V, V– = GND). In this configuration, the analog signal range is 0 V to 0 V (since VANALOG = V– to (V+ – 5) V = 0 V to 0 V), so it must be used with level-shifted inputs or in unipolar applications where signals stay near mid-supply. For full-range analog handling, dual supplies (e.g., V+ = +12 V, V– = –5 V) are required. Refer to the DG613DY-T1 specification table for unipolar supply performance.
How does the DG613DY-T1 achieve its low 2 pC charge injection?
The DG613DY-T1 achieves ±2 pC typical charge injection through matched transistor geometry, optimized channel doping, and precise layout symmetry in its lateral DMOS switch cells-minimizing imbalance during gate transition. This is further enhanced by the D/CMOS process's integrated level translators and low-capacitance interconnects. Verified via CL = 1 nF test condition per DG613DY-T1 datasheet Figure 3, this value directly enables sub-mV step error in sample-and-hold circuits without external correction.
Is the DG613DY-T1 pin-compatible with other devices in the DG611/DG612/DG613 family?
Yes, the DG613DY-T1 shares identical 16-pin narrow SOIC pinout with DG611DY-T1 and DG612DY-T1, including V+, V–, GND, VL, IN1–IN4, S1–S4, and D1–D4 assignments. However, truth table behavior differs: DG613DY-T1 activates SW1/SW4 on logic HIGH and SW2/SW3 on logic LOW, whereas DG611/DG612 are complementary single-throw. Swapping part numbers requires logic inversion or firmware update to maintain function. All three use the same DG613DY-T1 physical footprint.
What thermal derating applies to the DG613DY-T1 in SOIC package?
The DG613DY-T1 in 16-pin narrow SOIC has a power dissipation limit of 600 mW at TA ≤ 75 °C. Above 75 °C, power must be linearly derated at 7.6 mW/°C per the datasheet. At 105 °C ambient, maximum allowable dissipation drops to 372 mW. This assumes proper PCB copper area (≥1 cm² per pad) and still-air conditions. Exceeding derated limits risks parametric shift or long-term reliability degradation in the DG613DY-T1.
DG613DY-T1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Switch Circuit:
- SPST - NO/NC
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 4
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- 2Ohm
- Voltage - Supply, Single (V+):
- 10V ~ 18V
- Voltage - Supply, Dual (V±):
- ±10V ~ 15V
- Switch Time (Ton, Toff) (Max):
- 35ns, 25ns
- -3db Bandwidth:
- 500MHz
- Charge Injection:
- 4pC
- Channel Capacitance (CS(off), CD(off)):
- 3pF, 2pF
- Current - Leakage (IS(off)) (Max):
- 250pA
- Crosstalk:
- -87dB @ 10MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DG613DY-T1 FAQ
1.How can I place an order for DG613DY-T1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DG613DY-T1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG613DY-T1 reliable?
The price and inventory of DG613DY-T1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG613DY-T1 is usually 5 days.
3.What payment methods are accepted for DG613DY-T1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG613DY-T1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG613DY-T1?
DG613DY-T1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG613DY-T1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG613DY-T1?
For technical support, including DG613DY-T1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG613DY-T1 requirements.
6.How does Aetrix verify that DG613DY-T1 is sourced from the original manufacturer or authorized distributors?
All DG613DY-T1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG613DY-T1 meets industry standards.
7.What is the process for return or replacement of DG613DY-T1?
All DG613DY-T1 units undergo pre-shipment inspection (PSI). If there is an issue with DG613DY-T1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG613DY-T1 part is unused and in its original packaging.
Return procedure for DG613DY-T1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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