Vishay Siliconix DG613DY-T1-E3
- Part No.:
- DG613DY-T1-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG613DY-T1-E3.pdf
- Description:
- IC SWITCH SPST X 4 45OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG613DY-T1-E3 from Vishay Siliconix is a high-speed, low-glitch quad analog switch IC with two normally open (NO) and two normally closed (NC) SPST switches, enabling configurable 4×SPST, 2×SPDT, or 1×DPDT operation. It features 12 ns turn-on time, 18 Ω RDS(on), ±2 pC charge injection, 500 MHz bandwidth, and operates from ±5 V to ±10.5 V dual supplies or 5–21 V single supply. It is used in pixel-rate video switching and GaAs FET driver circuits.
For engineers reviewing the DG613DY-T1-E3 datasheet, DG613DY-T1-E3 pinout, DG613DY-T1-E3 application, or DG613DY-T1-E3 equivalent, key selection criteria include guaranteed 12 ns tON, low 2 pC charge injection for sample-and-hold accuracy, 500 MHz small-signal bandwidth, logic-level compatibility (VIL ≤ 1 V, VIH ≥ 4 V), and SOIC-16 package thermal performance (600 mW at TA ≤ 75 °C).
Technical Context
The DG613DY-T1-E3 integrates four independent lateral DMOS analog switches fabricated on Vishay's proprietary D/CMOS process, combining n-channel DMOS FETs with low-power CMOS control logic and drivers. An epitaxial layer prevents latch-up, and internal clamping diodes protect against overvoltage on S/D/IN pins beyond V+ or V−.
Its truth table defines complementary switching: logic low (≤1 V) turns SW1/SW4 OFF and SW2/SW3 ON; logic high (≥4 V) reverses states. The device supports bidirectional analog conduction when ON and blocks up to 16 Vp-p when OFF, with analog signal range specified from V− to (V+) − 5 V under recommended operating conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| tON | 12 ns typical - enables sub-83 MHz switching cycles without aperture error accumulation in fast sampling systems. |
| RDS(on) | 18 Ω typical at V+ = 15 V, V− = −3 V - ensures low insertion loss and minimal signal attenuation in 50 Ω video or RF paths. |
| Charge injection | ±2 pC maximum - limits step-induced offset errors in precision sample-and-hold and switched-capacitor filter applications. |
| Bandwidth | 500 MHz - supports full-spectrum transmission of NTSC/PAL composite video and high-definition pixel clock signals. |
| OIRR | 74 dB at 5 MHz - provides strong isolation between active and inactive channels in multi-source video routing. |
| VANALOG range | V− to (V+) − 5 V - allows rail-to-rail analog signal handling with headroom for logic-compatible control margins. |
| Supply range | V+ = 5–21 V, V− = −10 to 0 V - supports flexible unipolar or bipolar operation in industrial and communications equipment. |
Pinout & Package
DG613DY-T1-E3 is housed in a 16-pin narrow SOIC package (JEDEC MS-012), 3.9 mm wide, with 1.27 mm pitch, rated for 600 mW power dissipation at TA ≤ 75 °C and derated linearly above that temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 (IN1–IN4) | Digital control inputs | CMOS-compatible logic inputs driving respective switches; VIL ≤ 1 V, VIH ≥ 4 V define valid states. |
| 5, 6, 13, 14 (S1–S4) | Switch source terminals | Analog input nodes for each SPST switch; bidirectional conduction path when enabled. |
| 7, 8, 11, 12 (D1–D4) | Switch drain terminals | Analog output nodes; connect to load or next stage; support ±16 Vp-p blocking when OFF. |
| 9 (V−) | Negative supply rail | Bias reference for NMOS portion of DMOS switches; must be ≥ −10 V and ≤ 0.3 V relative to GND. |
| 10 (GND) | Ground reference | Common return for digital logic (VL), analog circuitry, and substrate; critical for minimizing ground bounce. |
| 15 (V+) | Positive supply rail | Bias reference for PMOS portion; supports 5–21 V operation; sets upper limit of analog signal swing. |
| 16 (VL) | Logic supply voltage | Independent 4–V+ logic rail; decouples digital switching noise from analog path and enables level translation. |
Key Features
| Feature | Design Value |
|---|---|
| Configurable switch topology | Two NO + two NC SPST elements allow hardware-defined reconfiguration as 4×SPST, 2×SPDT, or 1×DPDT without external components. |
| Low glitch energy | Guaranteed ≤4 pC charge injection and 12 ns tON/8 ns tOFF minimize transient artifacts during video pixel switching and DAC deglitching. |
| High off-isolation | 74 dB OIRR at 5 MHz ensures minimal crosstalk between background and overlay video sources in title-generation circuits. |
| Wide analog bandwidth | 500 MHz small-signal bandwidth preserves edge integrity in 1080p/60Hz pixel-clock routing and GaAs FET gate drive waveforms. |
| Latch-up immunity | Epitaxial substrate construction eliminates risk of destructive latch-up under transient overvoltage or ESD stress. |
Applications
| Pixel-Rate Video Switching | GaAs FET Driver |
|---|---|
|
Use Scenario: Overlaying text or graphics onto live video streams in broadcast encoders and set-top boxes. IC Role / Device Role / Timing Role: DG613DY-T1-E3 acts as a glitch-free analog multiplexer selecting between background and title video sources synchronized to pixel clock. Use Value: 500 MHz bandwidth and <12 ns propagation delay preserve chroma/luma timing alignment; ±2 pC charge injection prevents visible halos at transition edges. |
Use Scenario: High-speed RF switching in phased-array radar transceivers requiring nanosecond-scale GaAs FET gate control. IC Role / Device Role / Timing Role: DG613DY-T1-E3 provides complementary 0 V / −8 V gate drive to GaAs FETs via its NO/NC switch pairs, enabling precise RF path enable/disable. Use Value: 12 ns tON and 8 ns tOFF support >40 MHz RF modulation rates; low RDS(on) minimizes gate drive power loss across large switch arrays. |
| Fast Sample-and-Hold Circuit | Disk/Tape Drive Head Selection |
|
Use Scenario: Precision data acquisition in automated test equipment capturing fast transient waveforms. IC Role / Device Role / Timing Role: DG613DY-T1-E3 serves as the sampling switch in a high-speed S/H front-end, directly interfacing with low-leakage hold capacitors. Use Value: ±2 pC charge injection eliminates step errors; 18 Ω RDS(on) reduces settling time; 74 dB off-isolation prevents hold capacitor droop from adjacent channel coupling. |
Use Scenario: Selecting between multiple read/write heads in enterprise-class hard disk drives and tape storage subsystems. IC Role / Device Role / Timing Role: DG613DY-T1-E3 routes analog servo and data signals between controller ASIC and selected head assembly. Use Value: Bidirectional conduction supports both write-current drive and read-signal sensing; 16 Vp-p blocking capability handles head coil back-EMF spikes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4617ESE+ | Single-supply only (2.7–12 V); 10 Ω RDS(on); 300 MHz bandwidth; no negative supply support. | Suitable for portable battery-powered systems but cannot replicate DG613DY-T1-E3's bipolar rail operation or 500 MHz video bandwidth. | Select MAX4617ESE+ only when unipolar supply and lower on-resistance outweigh need for wide analog range and high-frequency fidelity. |
| ADG1412BRUZ | 4-channel SPST; 1.3 Ω RDS(on); 170 MHz bandwidth; requires ≥10 V supply for full 16 Vp-p signal swing. | Better for precision instrumentation where ultra-low on-resistance matters more than video bandwidth or charge injection. | Choose ADG1412BRUZ for low-distortion audio or sensor front-ends; avoid for pixel-rate video due to 170 MHz bandwidth limitation. |
Compared with MAX4617ESE+ and ADG1412BRUZ, DG613DY-T1-E3 uniquely balances high-speed (500 MHz), low-glitch (±2 pC), and dual-supply flexibility (V− to −10 V) - making it irreplaceable in sync-locked video overlay and GaAs FET driver designs where all three attributes are simultaneously required.
Availability
DG613DY-T1-E3 is available at Aetrix Electronics and suitable for pixel-rate video switching, GaAs FET driver circuits, fast sample-and-hold systems, disk/tape drive head selection, and DAC deglitching requiring stable component supply and long-term industrial availability.
Supply support for DG613DY-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete power MOSFETs, analog switches, diodes, and optoelectronics, with vertical integration across silicon design, wafer fabrication, and packaging.
The DG613DY-T1-E3 belongs to Vishay's high-speed analog switch product line, engineered specifically for applications demanding nanosecond switching, minimal charge injection, and robust bipolar supply operation in video, test, and RF infrastructure.
FAQ
What is the maximum analog signal voltage range supported by DG613DY-T1-E3?
DG613DY-T1-E3 supports an analog signal range from V− to (V+) − 5 V under recommended operating conditions. With V+ = 15 V and V− = −3 V, this yields −3 V to +10 V (13 Vp-p). Absolute maximum ratings allow up to ±16 Vp-p blocking, but sustained operation beyond the recommended range risks increased leakage or distortion. Always verify actual signal swing against the specific V+/V− rails used in your design.
Does DG613DY-T1-E3 require separate logic and analog supplies?
Yes, DG613DY-T1-E3 uses independent VL (logic supply) and V+/V− (analog supplies). VL must be between 4 V and V+, while V+ and V− define the analog signal range. This separation isolates digital switching noise from sensitive analog paths and enables level translation - a key enabler of its low-glitch performance in DG613DY-T1-E3.
Can DG613DY-T1-E3 be used in single-supply configurations?
Yes, DG613DY-T1-E3 supports single-supply operation with V− tied to GND and V+ between 5 V and 21 V. In this mode, the analog signal range becomes 0 V to (V+) − 5 V (e.g., 0–10 V at V+ = 15 V). Logic supply VL remains referenced to GND and must be ≥4 V. DG613DY-T1-E3 maintains full specification compliance including 12 ns tON and ±2 pC charge injection in this configuration.
What is the thermal derating behavior of DG613DY-T1-E3 in SOIC package?
DG613DY-T1-E3 in narrow SOIC has a power dissipation rating of 600 mW at ambient temperature ≤75 °C. Above 75 °C, it must be derated at 7.6 mW/°C - meaning at 100 °C ambient, maximum allowable power drops to 410 mW. This derating ensures junction temperature stays within safe limits; always calculate worst-case power (I²R + IQV) and confirm thermal margin using board layout and airflow conditions.
How does the DG613DY-T1-E3 truth table differ from DG611/DG612?
DG613DY-T1-E3 implements a complementary pair configuration: logic low (≤1 V) turns SW1/SW4 OFF and SW2/SW3 ON; logic high (≥4 V) reverses states. In contrast, DG611 is active-high (ON at logic high), while DG612 is active-low (ON at logic low). This dual-state architecture enables DG613DY-T1-E3 to realize SPDT/DPDT functions without external inverters - a functional distinction confirmed in the DG613DY-T1-E3 truth table and block diagram.
DG613DY-T1-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Switch Circuit:
- SPST - NO/NC
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 4
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- 2Ohm
- Voltage - Supply, Single (V+):
- 10V ~ 18V
- Voltage - Supply, Dual (V±):
- ±10V ~ 15V
- Switch Time (Ton, Toff) (Max):
- 35ns, 25ns
- -3db Bandwidth:
- 500MHz
- Charge Injection:
- 4pC
- Channel Capacitance (CS(off), CD(off)):
- 3pF, 2pF
- Current - Leakage (IS(off)) (Max):
- 250pA
- Crosstalk:
- -87dB @ 10MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DG613DY-T1-E3 FAQ
1.How can I place an order for DG613DY-T1-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for DG613DY-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG613DY-T1-E3 reliable?
The price and inventory of DG613DY-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG613DY-T1-E3 is usually 5 days.
3.What payment methods are accepted for DG613DY-T1-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG613DY-T1-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG613DY-T1-E3?
DG613DY-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG613DY-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG613DY-T1-E3?
For technical support, including DG613DY-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG613DY-T1-E3 requirements.
6.How does Aetrix verify that DG613DY-T1-E3 is sourced from the original manufacturer or authorized distributors?
All DG613DY-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG613DY-T1-E3 meets industry standards.
7.What is the process for return or replacement of DG613DY-T1-E3?
All DG613DY-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with DG613DY-T1-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG613DY-T1-E3 part is unused and in its original packaging.
Return procedure for DG613DY-T1-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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