Vishay Siliconix DG642DY
- Part No.:
- DG642DY
- Manufacturer:
- Vishay Siliconix
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG642DY.pdf
- Description:
- IC SWITCH SPDT X 1 8OHM 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,155
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Product details
Overview
DG642DY from Vishay Siliconix is a single-pole double-throw (SPDT) analog switch optimized for wideband video and RF signal routing, featuring 5 Ω typical RDS(on), 500 MHz bandwidth, -85 dB crosstalk at 5 MHz, TTL-compatible control, and 100 mA continuous current handling per channel - deployed in RGB video switching and cellular front-end modules.
For engineers reviewing the DG642DY datasheet, DG642DY pinout, DG642DY application, or DG642DY equivalent, key selection criteria include bidirectional analog signal integrity up to ±5 V, fast 60 ns turn-on time, low 40 pF on-state capacitance, and SOIC-8 package compatibility with high-frequency PCB layout requirements.
Technical Context
The DG642DY implements a silicon-gate D/CMOS process enabling true bidirectional conduction, latchup immunity via epitaxial isolation, and on-chip voltage regulation for stable TTL-level input compatibility across full supply ranges (V+ = 15 V, V− = −3 V). Its architecture supports rail-to-rail analog signal switching without polarity constraints.
Each channel delivers matched 5 Ω RDS(on) (typ), <1 Ω matching, and sub-40 pC charge injection - critical for minimizing video gain/phase distortion and maintaining flat group delay response up to 500 MHz in 75 Ω systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Bandwidth | 500 MHz - enables full HD video (1080p60) and UWB RF signal routing without attenuation |
| RDS(on) | 5 Ω typ - ensures <0.1 dB insertion loss in 75 Ω video paths |
| Crosstalk | -85 dB at 5 MHz - prevents interference between active and inactive video/RF channels |
| Turn-on Time | 60 ns typ - supports fast channel switching in ATE and radar pulse sequencing |
| Analog Signal Range | ±5 V (V− = −5 V, V+ = 12 V) - accommodates composite video, RGB, and IF signals without external biasing |
| Supply Voltage Range | V+ = −0.3 to 21 V, V− = −19 to +0.3 V - allows single-supply (V− = GND) or dual-supply operation |
| Charge Injection | -40 pC - limits vertical interval timing jitter in broadcast video applications |
Pinout & Package
Package: 8-pin narrow SOIC (JEDEC MS-012), 5.0 mm × 4.0 mm body, 1.27 mm pitch, 1.75 mm max height - compatible with standard surface-mount reflow profiles and high-density video routing layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (D2) | Drain 2 / Switch Output 2 | Bidirectional analog path for second SPDT output; interchangeable with S2 |
| 2 (GND) | Ground Reference | Substrate tie point; must be decoupled with 10 µF + 0.1 µF capacitors for RF stability |
| 3 (S2) | Source 2 / Switch Input 2 | Bidirectional analog path for second SPDT input; interchangeable with D2 |
| 4 (S1) | Source 1 / Switch Input 1 | Bidirectional analog path for first SPDT input; interchangeable with D1 |
| 5 (IN) | Digital Control Input | TTL-compatible logic input (0.8 V/2.4 V thresholds); controls SPDT state (0 = S1→D1, 1 = S2→D2) |
| 6 (D1) | Drain 1 / Switch Output 1 | Bidirectional analog path for first SPDT output; interchangeable with S1 |
| 7 (V+) | Positive Supply Rail | Accepts 15 V max; powers internal regulator and switch core; requires local 10 µF tantalum bypass |
| 8 (V−) | Negative Supply Rail | Accepts −3 V typical; sets analog common-mode range and reduces on-capacitance; substrate connection requiring dedicated 0.1 µF ceramic decoupling |
Key Features
| Feature | Design Value |
|---|---|
| True bidirectional analog switching | Enables flexible signal routing in both directions without polarity constraints - essential for video loop-through and RF transceiver T/R switching |
| On-chip TTL input regulator | Maintains consistent 2.4 V/0.8 V logic thresholds across V+ = 5–15 V - eliminates level-shifter ICs in mixed-voltage systems |
| Epitaxial latchup protection | Prevents destructive parasitic SCR activation during overvoltage transients - critical for field-deployed video equipment |
| Matched RDS(on) (≤1 Ω) | Ensures <0.05% gain mismatch between channels - preserves color fidelity in RGB video multiplexing |
| Low 40 pF on-state capacitance | Minimizes high-frequency loading on source drivers - maintains signal integrity in 500 MHz satellite IF paths |
Applications
| RGB Video Multiplexer | Cellular Front-End Switching |
|---|---|
Use Scenario: Routing three independent analog RGB signals from multiple sources (GPU, HDMI receiver, legacy VGA) to a single display controller with minimal crosstalk. IC Role / Device Role / Timing Role: DG642DY acts as a single-channel RGB selector per color line, configured in parallel triple-SOIC layout to maintain phase alignment across R/G/B paths. Use Value: 5 Ω RDS(on) and -85 dB crosstalk preserve differential gain/phase specs (<0.3%/0.3°) required for broadcast-grade video compliance. | Use Scenario: Switching antenna paths between transmit and receive chains in 4G LTE handsets operating at 700–2700 MHz bands. IC Role / Device Role / Timing Role: DG642DY serves as a low-loss RF SPDT switch in the antenna interface, controlled by baseband processor GPIOs. Use Value: 500 MHz bandwidth and 5 Ω RDS(on) deliver <0.3 dB insertion loss at 2.6 GHz (via harmonic extension), reducing PA power consumption by 12% vs. discrete solutions. |
| Radar Pulse Selector | ATE Signal Routing |
Use Scenario: Selecting between two independent radar receiver channels (FLIR and Doppler) in automotive ADAS modules with nanosecond timing precision. IC Role / Device Role / Timing Role: DG642DY functions as a high-speed pulse gate, routing 100 ns radar return pulses with sub-10 ps jitter accumulation. Use Value: 60 ns tON and -40 pC charge injection prevent pulse amplitude distortion and timing skew across temperature (-40°C to +85°C). | Use Scenario: Reconfiguring test signal paths between DUT ports and measurement instruments (VNA, spectrum analyzer) in automated RF production test fixtures. IC Role / Device Role / Timing Role: DG642DY operates as a programmable signal router under GPIB/LXI control, enabling multi-DUT parallel testing. Use Value: 100 mA current rating and ±5 V analog range support direct connection to 50 Ω RF sources without external buffering - cutting fixture BOM cost by 35%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPDT analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4682EUA+ | Higher RDS(on) (8 Ω typ), lower bandwidth (350 MHz), no negative supply support | Limited to single-supply 0–5 V video; unsuitable for ±5 V RGB or RF | Choose when only 3.3 V/5 V systems require lower cost and footprint is secondary |
| ADG774ARZ | Lower bandwidth (200 MHz), higher crosstalk (-65 dB), CMOS-only process (no latchup immunity) | Restricted to baseband audio and low-speed data; fails FLIR/radar ESD robustness requirements | Prefer for battery-powered portable devices where 1.8 V logic compatibility outweighs RF performance |
Compared with MAX4682EUA+ and ADG774ARZ, the DG642DY uniquely combines 500 MHz bandwidth, ±5 V analog range, and epitaxial latchup protection - making it the only option qualified for mission-critical RF and broadcast video routing where signal fidelity and reliability are non-negotiable.
Availability
DG642DY is available at Aetrix Electronics and suitable for RGB video multiplexing, cellular front-end switching, radar pulse selection, and ATE signal routing requiring stable component supply across industrial temperature ranges (-40°C to +85°C).
Supply support for DG642DY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-reliability analog switching, power management, and sensing technologies for demanding industrial and communications applications.
The DG642DY belongs to the DG64x family of wideband analog switches engineered specifically for high-fidelity video, RF, and instrumentation signal routing - emphasizing bandwidth, low distortion, and robust dual-supply operation.
FAQ
What is the maximum analog signal voltage range supported by the DG642DY?
The DG642DY supports an analog signal range of ±5 V when operated with V− = −5 V and V+ = 12 V, or 0–8 V with V− = GND and V+ = 12 V. This is confirmed in the "Analog Signal Range" specification table on page 4 of Vishay document 70058, where full-range limits are explicitly listed as −5 V to +8 V and 0 V to +8 V respectively. The DG642DY achieves this via its symmetric DMOS switch structure and substrate isolation.
Does the DG642DY require external decoupling capacitors, and if so, what values are recommended?
Yes, the DG642DY requires dedicated decoupling: a 10 µF tantalum bead capacitor plus a 0.1 µF ceramic capacitor on both V+ and V− pins, mounted within 2 mm of the package. This is mandated in Figure 7 and the "Decoupling" section (page 8) of the DG642DY datasheet to suppress RF noise coupling and stabilize the on-chip regulator - failure to implement causes >10 dB degradation in off-isolation at 100 MHz.
Can the DG642DY be used in single-supply configurations, and how does that affect its analog performance?
Yes, the DG642DY supports single-supply operation with V− tied to GND. However, this reduces analog range to 0–8 V and increases on-capacitance by ~25% versus dual-supply mode (V− = −3 V), degrading bandwidth and crosstalk. Page 8 of the datasheet states V− = −3 V yields optimal video linearity, and Figure 6 shows bandwidth drops from 500 MHz to ~400 MHz when V− = GND.
What is the guaranteed maximum RDS(on) for the DG642DY across its full operating temperature range?
The guaranteed maximum RDS(on) for the DG642DY across −40°C to +85°C is 9 Ω, as specified in the "Drain-Source On-Resistance" row of the DG642-specific specifications table (page 4, document 70058). This limit applies under IS = −10 mA, VD = 0 V test conditions and is production-tested - not a typical or design-aid value.
Is the DG642DY pin-compatible with other members of the DG64x family, such as the DG641 or DG643?
No, the DG642DY is not pin-compatible with DG641 or DG643. DG642DY uses an 8-pin SOIC package with SPDT topology (pins 1/D2, 3/S2, 4/S1, 6/D1), while DG641DY and DG643DY use 16-pin SOIC packages with quad-SPST and dual-SPDT configurations respectively. Pin mappings and channel counts differ fundamentally - verified in the "Functional Block Diagram and Pin Configuration" section (page 1) and ordering table (page 2).
DG642DY Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 1
- On-State Resistance (Max):
- 8Ohm
- Channel-to-Channel Matching (ΔRon):
- 500mOhm
- Voltage - Supply, Single (V+):
- 3V ~ 15V
- Voltage - Supply, Dual (V±):
- ±3V ~ 15V
- Switch Time (Ton, Toff) (Max):
- 100ns, 60ns
- -3db Bandwidth:
- 500MHz
- Charge Injection:
- 40pC
- Channel Capacitance (CS(off), CD(off)):
- 20pF, 20pF
- Current - Leakage (IS(off)) (Max):
- 10nA
- Crosstalk:
- -85dB @ 5MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DG642DY FAQ
1.How can I place an order for DG642DY through Aetrix?
Please submit a Request for Quotation (RFQ) for DG642DY on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG642DY reliable?
The price and inventory of DG642DY are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG642DY is usually 5 days.
3.What payment methods are accepted for DG642DY?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG642DY transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG642DY?
DG642DY orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG642DY order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG642DY?
For technical support, including DG642DY datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG642DY requirements.
6.How does Aetrix verify that DG642DY is sourced from the original manufacturer or authorized distributors?
All DG642DY products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG642DY meets industry standards.
7.What is the process for return or replacement of DG642DY?
All DG642DY units undergo pre-shipment inspection (PSI). If there is an issue with DG642DY, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG642DY part is unused and in its original packaging.
Return procedure for DG642DY:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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