Vishay Siliconix DG9461DY
- Part No.:
- DG9461DY
- Manufacturer:
- Vishay Siliconix
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG9461DY.pdf
- Description:
- IC SWITCH SPDT X 1 60OHM 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG9461DY from Vishay Siliconix is a low-voltage single-pole/double-throw (SPDT) CMOS analog switch in SOIC-8 package, featuring 40 Ω typical rDS(on) at 5 V, 35 ns turn-on time, and 20 ns turn-off time. It operates from +2.7 V to +5 V, supports bidirectional signal switching up to the supply rail, and guarantees break-before-make timing-ideal for precision sample-and-hold circuits in portable test equipment.
For engineers reviewing the DG9461DY datasheet, DG9461DY pinout, DG9461DY application, or DG9461DY equivalent, key selection criteria include on-resistance matching (ΔrDS(on) ≤ 2 Ω), ultra-low charge injection (1–2 pC), sub-100 pA channel-on leakage at 25 °C, and guaranteed ESD protection >2000 V per Method 3015.7.
Technical Context
The DG9461DY implements a monolithic CMOS SPDT switch architecture built on Vishay's BCD-15 low-voltage process, with epitaxial layer latchup prevention. Its digital control interface accepts TTL/CMOS logic levels (0.8 V low, 2.4 V high) and drives both NO and NC paths with symmetrical conduction when enabled.
Break-before-make timing is guaranteed (td ≤ 10 ns at 5 V), and all analog terminals (COM, NO, NC) tolerate signals from –0.3 V to (V+ + 0.3 V). The device supports full analog signal range from 0 to V+ (0–5 V at 5 V supply) with off-isolation of –74 dB at 1 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| rDS(on) | 30 Ω typ @ 5 V - enables low insertion loss and minimal signal distortion in audio and data paths |
| tON / tOFF | 35 ns / 20 ns @ 5 V - supports high-speed multiplexing in sampling systems up to ~10 MHz |
| QINJ | 1–2 pC - ensures <1 LSB error in 12-bit 1 MSPS SAR ADC sample-and-hold front-ends |
| ICOM(on) | 200 pA max @ 25 °C - preserves accuracy in high-impedance sensor interfaces and precision integrators |
| OIRR | –74 dB @ 1 MHz - provides strong channel-to-channel isolation in multi-signal routing applications |
| V+ Range | +2.7 V to +12 V - allows operation from single Li-ion cell (3.0–3.7 V) or regulated 5 V rails |
| ESD Rating | >2000 V HBM (Method 3015.7) - meets basic handling robustness for board-level assembly |
Pinout & Package
Package: 8-pin narrow-body SOIC (SOIC-8), 150 mil width, RoHS-compliant lead finish (E3 suffix).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (IN) | Digital control input | Accepts TTL/CMOS logic; high = connect COM to NO, low = connect COM to NC |
| 2 (NO) | Normally open switch terminal | Open-circuit when IN = low; connects to COM when IN = high |
| 3 (NC) | Normally closed switch terminal | Connected to COM when IN = low; open when IN = high |
| 4 (GND) | Analog and digital ground reference | Common return for power, logic, and signal paths; must be low-impedance |
| 5 (COM) | Common analog port | Bidirectional signal path shared between NO and NC; handles full 0–V+ range |
| 6 (V+) | Positive supply rail | Powers internal logic and switch core; decoupling capacitor required at pin |
| 7, 8 | No connect (NC) | Internally unconnected; must remain floating or tied to GND per layout best practice |
Key Features
| Feature | Design Value |
|---|---|
| Break-before-make guarantee | Ensures no momentary short between NO and NC during state transition, critical for avoiding signal glitches in mux-based systems |
| Low charge injection (1–2 pC) | Minimizes voltage step on hold capacitors, enabling accurate DC-coupled sampling without correction circuitry |
| Matched on-resistance (ΔrDS(on) ≤ 2 Ω) | Reduces gain error and THD in differential or dual-path signal routing where path symmetry matters |
| Full rail-to-rail analog range | Supports unipolar 0–5 V or bipolar ±2.5 V signals (with appropriate biasing), simplifying front-end design |
| TTL/CMOS-compatible logic threshold | Interfacing directly with microcontrollers and FPGAs without level-shifting, reducing BOM count |
Applications
| Battery-Powered Test Equipment | Portable Medical Sensors |
|---|---|
Use Scenario: Multiplexing multiple sensor inputs (ECG leads, temperature probes) into a single ADC channel in handheld diagnostic devices. IC Role / Device Role / Timing Role: Analog SPDT switch routing biopotential signals with minimal added noise and offset. Use Value: 200 pA max ICOM(on) prevents loading of high-impedance electrode interfaces; 35 ns switching enables rapid channel scanning. | Use Scenario: Selecting between calibration references and active sensor outputs in wearable glucose monitors. IC Role / Device Role / Timing Role: Precision analog switch isolating reference voltages from measurement paths during auto-calibration cycles. Use Value: 1 pC charge injection avoids disturbing small hold capacitors (<10 pF); break-before-make prevents reference shorting. |
| Industrial Data Acquisition Modules | Communications Baseband Signal Routing |
Use Scenario: Channel selection in 16-channel thermocouple input modules with cold-junction compensation. IC Role / Device Role / Timing Role: Low-leakage SPDT switch enabling high-impedance thermocouple voltage acquisition without gain drift. Use Value: <100 pA off-leakage (INO/NC(off)) maintains µV-level accuracy over temperature; SOIC-8 eases manual rework. | Use Scenario: Antenna diversity switching and IF signal path selection in LTE femtocell baseband boards. IC Role / Device Role / Timing Role: High-isolation analog switch routing 0–5 V baseband I/Q signals between transceiver chains. Use Value: –74 dB off-isolation at 1 MHz suppresses crosstalk between parallel receive paths; 40 Ω rDS(on) limits insertion loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPDT analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4617ESA+ | Higher rDS(on) (60 Ω typ), slower tON (75 ns), but lower QINJ (0.5 pC); requires dual supply for bipolar signal support | Preferred in ultra-low-charge-injection precision instrumentation where speed is secondary | Select MAX4617ESA+ only if sub-1 pC injection is mandatory and 5 V single-supply operation is not required |
| ADG746BRUZ | Lower rDS(on) (2.5 Ω typ), faster switching (12 ns), but higher ICOM(on) (2 nA) and no guaranteed break-before-make | Suitable for high-speed digital signal routing where leakage tolerance >1 nA is acceptable | Choose ADG746BRUZ when bandwidth >50 MHz is needed and leakage-induced offset can be calibrated out |
Compared with MAX4617ESA+ and ADG746BRUZ, the DG9461DY delivers balanced performance: moderate speed and on-resistance with guaranteed break-before-make and industry-standard ESD robustness-making it optimal for cost-sensitive, battery-powered industrial and medical mux designs where reliability and ease of use are prioritized over extreme specs.
Availability
DG9461DY is available at Aetrix Electronics and suitable for battery-operated systems, portable test equipment, and sample-and-hold circuits requiring stable component supply across extended temperature ranges (–40 °C to +85 °C).
Supply support for DG9461DY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete MOSFETs, diodes, optoelectronics, and precision analog switches, with emphasis on high-reliability, high-performance components for industrial and automotive markets.
The DG9461 belongs to Vishay's low-voltage analog switch product line, designed specifically for portable, battery-powered applications demanding low power, small footprint, and robust signal integrity-especially where rail-to-rail analog switching and guaranteed timing behavior are essential.
FAQ
What is the maximum analog signal voltage supported by the DG9461DY?
The DG9461DY supports analog signals from 0 V to V+, where V+ ranges from +2.7 V to +12 V. At V+ = 5 V, the full analog range is 0–5 V. Input signals exceeding V+ or going below –0.3 V are clamped by internal diodes, so the DG9461DY must be used within these absolute limits to avoid damage or increased leakage. This rail-to-rail capability makes the DG9461DY suitable for unipolar sensor interfaces without external level-shifting.
Does the DG9461DY require external pull-up or pull-down resistors on its IN pin?
No, the DG9461DY does not require external pull-up or pull-down resistors on the IN pin. Its digital input is TTL/CMOS compatible with defined thresholds: logic low ≤ 0.8 V and logic high ≥ 2.4 V at V+ = 5 V. The input current is specified at ≤ 1 µA across temperature, so direct connection to microcontroller GPIO or FPGA output drivers is fully supported. This simplifies PCB layout and reduces component count in the DG9461DY application.
Is break-before-make timing guaranteed for the DG9461DY, and what is its typical value?
Yes, break-before-make timing is guaranteed for the DG9461DY. Per the datasheet, the break-before-make interval (td) is specified as ≤ 10 ns at V+ = 5 V and room temperature. This guarantee is process-verified and ensures no overlap between NO and NC conduction states during switching-critical for preventing short-circuits in sensitive analog routing. The DG9461DY's guaranteed td eliminates need for external timing control in systems relying on clean signal path isolation.
Can the DG9461DY be used with a 3.3 V supply, and how does performance change vs. 5 V?
Yes, the DG9461DY is fully specified for operation at 3.3 V (within its +2.7 V to +5 V range). At V+ = 3 V, rDS(on) increases to 50–140 Ω (vs. 30–75 Ω at 5 V), tON degrades to 50–200 ns (vs. 35–150 ns), and leakage remains within spec. The DG9461DY maintains functional compatibility and guaranteed break-before-make at 3.3 V, making it suitable for modern low-voltage microcontroller systems-though designers should verify on-resistance impact on signal fidelity in their specific DG9461DY application.
What is the thermal derating behavior of the DG9461DY above 75 °C?
The DG9461DY must be derated at 6.5 mW/°C above 75 °C ambient temperature. Its maximum power dissipation is 400 mW in SOIC-8 at ≤75 °C. Above that, allowable power drops linearly-for example, at 100 °C ambient, max dissipation is reduced to 400 mW – (25 °C × 6.5 mW/°C) = 237.5 mW. This derating applies to total package power, including I²R losses and supply current. Thermal design for the DG9461DY should ensure junction temperature stays within –40 °C to +125 °C storage limit.
DG9461DY Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 1
- On-State Resistance (Max):
- 60Ohm
- Channel-to-Channel Matching (ΔRon):
- 400mOhm
- Voltage - Supply, Single (V+):
- 2.7V ~ 5V
- Voltage - Supply, Dual (V±):
- -
- Switch Time (Ton, Toff) (Max):
- 75ns, 50ns
- -3db Bandwidth:
- -
- Charge Injection:
- 2pC
- Channel Capacitance (CS(off), CD(off)):
- 7pF
- Current - Leakage (IS(off)) (Max):
- 100pA
- Crosstalk:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DG9461DY FAQ
1.How can I place an order for DG9461DY through Aetrix?
Please submit a Request for Quotation (RFQ) for DG9461DY on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG9461DY reliable?
The price and inventory of DG9461DY are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG9461DY is usually 5 days.
3.What payment methods are accepted for DG9461DY?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG9461DY transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG9461DY?
DG9461DY orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG9461DY order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG9461DY?
For technical support, including DG9461DY datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG9461DY requirements.
6.How does Aetrix verify that DG9461DY is sourced from the original manufacturer or authorized distributors?
All DG9461DY products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG9461DY meets industry standards.
7.What is the process for return or replacement of DG9461DY?
All DG9461DY units undergo pre-shipment inspection (PSI). If there is an issue with DG9461DY, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG9461DY part is unused and in its original packaging.
Return procedure for DG9461DY:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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