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Home > Products > Integrated Circuits (ICs) > Memory > Memory

Analog Devices Inc./Maxim Integrated DS1265Y-100

Name: DS1265Y-100
Brand: Analog Devices Inc./Maxim Integrated
SKU: DS1265Y-100
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: DS1265Y-100

Manufacturer:: Analog Devices Inc./Maxim Integrated

Category:: Memory

Package:: 36-DIP Module (0.610", 15.49mm)

Datasheet:: DS1265Y-100.pdf

Description:: IC NVSRAM 8MBIT PARALLEL 36EDIP

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Product details

Overview

DS1265Y-100 from Maxim Integrated (now Analog Devices) is a 8 Mbit (1,048,576 × 8) nonvolatile static RAM with integrated lithium battery backup, full ±10% V_CC operation (4.5V–5.5V), 70 ns read/write access time, and guaranteed 10-year data retention without external power. It serves as a drop-in SRAM replacement in systems requiring persistent memory during power loss, such as industrial controllers and metering hardware.

For engineers reviewing the DS1265Y-100 datasheet, DS1265Y-100 pinout, DS1265Y-100 application, or DS1265Y-100 equivalent, key selection considerations include its self-contained power-fail detection circuitry, automatic write protection below 4.25 V, 36-pin 740-mil extended DIP package, and compatibility with standard microprocessor bus timing.

Technical Context

The DS1265Y-100 implements autonomous power monitoring via an internal voltage comparator that triggers at V_TP = 4.25 V (min), switching to lithium backup and enabling unconditional write protection. Its CMOS architecture supports unlimited write cycles and requires no external support circuitry for NV operation.

It operates in three distinct modes: normal read/write (V_CC ≥ 4.5 V), data retention (V_CC < ~3.0 V, lithium active), and transitional power-down/power-up (V_CC between 3.0 V and 4.5 V), with t_PD = 1.5 µs fail-detect latency and t_REC = 125 ms recovery to full write protection.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Size	8,388,608-bit (1,048,576 × 8) - directly replaces standard 1-Mbyte SRAMs without address decoding changes
Access Time	70 ns - meets timing requirements for 14 MHz bus interfaces with no wait states
V_CC Range	4.5 V to 5.5 V (±10%) - tolerates wide-input unregulated supplies common in industrial power rails
Data Retention	10 years minimum without power - enabled by sealed lithium cell disconnected until first V_CC application
Write Protection Threshold	V_TP = 4.25 V (min) - initiates automatic write lock before system brownout corrupts data
Operating Temperature	0°C to +70°C (commercial) - validated for stable operation across ambient temperature swings in enclosed enclosures
Standby Current	100–200 µA (CE = V_CC−0.5 V) - enables low-power hold mode in battery-backed systems

Pinout & Package

DS1265Y-100 is housed in a 36-pin 740-mil Extended Dual In-line Package (EDIP), RoHS-compliant, wave- or hand-solderable only. Pin layout follows industry-standard parallel SRAM interface with dedicated control, address, and bidirectional data lines.

Pin/Terminal	Circuit Role	Design Meaning
A0–A19	Address Inputs	20-bit address bus interface supporting full 1-Mword addressing; compatible with 80Cxx/8051/Z80-style address latching
DQ0–DQ7	Bidirectional Data I/O	8-bit parallel data path; high-impedance when CE or OE inactive, eliminating need for external bus transceivers
CE	Chip Enable	Active-low chip select; must be stable before address setup; controls device participation in bus cycle
WE	Write Enable	Active-low write strobe; falling edge initiates write; rising edge terminates it; disables outputs during write if OE active
OE	Output Enable	Active-low output enable; used only during reads; high during writes prevents bus contention
V_CC	Power Supply	+5 V supply input; monitored continuously for decay; powers internal logic and RAM array
GND	Ground	Reference return path for all signals and internal circuitry; requires low-impedance connection
NC	No Connect	Pins 12, 23, 24, and 34 are unconnected; must remain floating or tied to GND per layout guidelines

Key Features

Feature	Design Value
Automatic Power-Fail Detection	Internal comparator triggers write protection and lithium switchover within 1.5 µs of V_CC crossing 4.25 V threshold
Lithium Freshness Seal	Lithium cell electrically isolated until first V_CC > V_TP, preserving full 10-year retention capacity from shipment
Unlimited Write Cycles	No endurance limit on SRAM core - eliminates wear-leveling firmware and write-cycle counting overhead
Full Bus Compatibility	Standard SRAM timing (t_ACC, t_WC, t_OE) matches 70 ns microprocessor buses without glue logic
Self-Contained Backup	No external capacitors, regulators, or supervisory ICs required - reduces BOM count and PCB area

Applications

Industrial Data Loggers	Smart Energy Meters
Use Scenario: Continuous logging of sensor readings and event timestamps during grid outages or maintenance windows. IC Role / Device Role / Timing Role: Nonvolatile SRAM buffer storing up to 1 Mbyte of timestamped operational data with zero write latency. Use Value: Guarantees data integrity across uncontrolled power cycles without filesystem layer or flash translation.	Use Scenario: Storing tariff schedules, consumption registers, and tamper-event records in utility-grade electricity meters. IC Role / Device Role / Timing Role: Primary volatile memory with embedded backup, retaining critical billing data during battery-swaps or main power loss. Use Value: Meets ANSI C12.1 and IEC 62056 requirements for 10-year data retention without periodic refresh or external battery management.
Programmable Logic Controllers	Medical Diagnostic Equipment
Use Scenario: Holding ladder logic state, I/O mapping, and configuration parameters during controller reboot or firmware update. IC Role / Device Role / Timing Role: Fast-access configuration memory mapped into CPU address space, surviving cold starts and watchdog resets. Use Value: Eliminates boot-time reinitialization delays and ensures deterministic startup behavior after unexpected power interruption.	Use Scenario: Capturing real-time patient waveform buffers and calibration constants during imaging sessions where power continuity cannot be assumed. IC Role / Device Role / Timing Role: High-reliability scratchpad memory for time-critical acquisition engines interfacing with ADCs and FPGAs. Use Value: Provides sub-70 ns deterministic access and failsafe retention compliant with IEC 62304 Class C software safety requirements.

Industrial Data Loggers

Smart Energy Meters

Use Scenario: Continuous logging of sensor readings and event timestamps during grid outages or maintenance windows.

IC Role / Device Role / Timing Role: Nonvolatile SRAM buffer storing up to 1 Mbyte of timestamped operational data with zero write latency.

Use Value: Guarantees data integrity across uncontrolled power cycles without filesystem layer or flash translation.

Use Scenario: Storing tariff schedules, consumption registers, and tamper-event records in utility-grade electricity meters.

IC Role / Device Role / Timing Role: Primary volatile memory with embedded backup, retaining critical billing data during battery-swaps or main power loss.

Use Value: Meets ANSI C12.1 and IEC 62056 requirements for 10-year data retention without periodic refresh or external battery management.

Programmable Logic Controllers

Medical Diagnostic Equipment

Use Scenario: Holding ladder logic state, I/O mapping, and configuration parameters during controller reboot or firmware update.

IC Role / Device Role / Timing Role: Fast-access configuration memory mapped into CPU address space, surviving cold starts and watchdog resets.

Use Value: Eliminates boot-time reinitialization delays and ensures deterministic startup behavior after unexpected power interruption.

Use Scenario: Capturing real-time patient waveform buffers and calibration constants during imaging sessions where power continuity cannot be assumed.

IC Role / Device Role / Timing Role: High-reliability scratchpad memory for time-critical acquisition engines interfacing with ADCs and FPGAs.

Use Value: Provides sub-70 ns deterministic access and failsafe retention compliant with IEC 62304 Class C software safety requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar nonvolatile SRAM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
DS1265AB-70+	Narrower V_CC range (4.75–5.25 V); higher write-protection threshold (4.50 V min); same 70 ns speed and 36-pin EDIP	Better suited for regulated 5 V systems where tighter supply tolerance is guaranteed	Select DS1265AB-70+ when board-level regulation ensures stable 5 V ±5%; otherwise DS1265Y-100 provides wider margin for unregulated inputs
STK12C68	Same 8 Mbit size and 70 ns speed but uses external capacitor-based backup; no integrated lithium; requires external supervisor	Lower cost but increases design complexity and reduces long-term reliability due to capacitor aging	Choose STK12C68 only if lithium-free design is mandated and capacitor lifetime modeling is performed

Compared with DS1265AB-70+ and STK12C68, DS1265Y-100 offers the widest V_CC tolerance (±10%) and fully autonomous backup-making it optimal for field-deployed equipment with variable input rails and zero-maintenance requirements.

Availability

DS1265Y-100 is available at Aetrix Electronics and suitable for industrial data loggers, smart energy meters, programmable logic controllers, and medical diagnostic equipment requiring stable component supply, long-lifecycle support, and guaranteed nonvolatile memory performance.

Supply support for DS1265Y-100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices (via acquisition of Maxim Integrated) designs high-reliability analog, mixed-signal, and nonvolatile memory solutions for demanding industrial, automotive, and medical applications.

The DS1265Y-100 belongs to Maxim's legacy nonvolatile SRAM product line, engineered specifically for systems needing seamless, zero-software-overhead memory persistence during unpredictable power interruptions.

FAQ

What is the guaranteed data retention period for DS1265Y-100 under zero-power conditions?

The DS1265Y-100 guarantees a minimum 10-year data retention period when operating in battery backup mode with no external power applied. This specification is assured through component selection, process control, and design-not measured per unit-but applies cumulatively from the moment V_CC is first applied and the lithium cell is activated. The DS1265Y-100 achieves this using a hermetically sealed lithium energy source disconnected until initial power-up.

Does DS1265Y-100 require external circuitry to manage battery backup or power-fail detection?

No, DS1265Y-100 requires no external circuitry for battery backup or power-fail detection. It integrates a precision voltage comparator, power-switching circuitry, and lithium cell within the 36-pin EDIP package. The DS1265Y-100 autonomously monitors V_CC, initiates write protection below 4.25 V, and switches to lithium power below ~3.0 V-all without external components or firmware intervention.

What is the difference between DS1265Y-100 and DS1265AB-70+ in terms of supply voltage tolerance?

The DS1265Y-100 supports a ±10% V_CC range (4.5 V to 5.5 V), while DS1265AB-70+ supports only ±5% (4.75 V to 5.25 V). This makes DS1265Y-100 more tolerant of unregulated or aging power supplies. Both share identical 70 ns access time, 36-pin EDIP packaging, and nonvolatile functionality-but DS1265Y-100's wider tolerance improves robustness in field-deployed industrial systems.

Can DS1265Y-100 be used in industrial temperature environments?

Yes, the DS1265Y-100 is available in an industrial temperature grade (DS1265Y-70IND+) rated for -40°C to +85°C operation. While the base DS1265Y-100 part number denotes commercial temperature range (0°C to +70°C), the IND-suffixed variant maintains full electrical specifications-including 70 ns access time and 4.25 V write-protection threshold-across the extended range, making DS1265Y-100 suitable for harsh-environment deployments when ordered with IND suffix.

How does DS1265Y-100 handle bus contention during write cycles?

During write cycles, DS1265Y-100 prevents bus contention by disabling its output drivers when WE is active (low), regardless of OE state. If OE is inadvertently active during a write, the DS1265Y-100 overrides it and forces outputs into high-impedance within t_ODW = 25 ns of WE's falling edge. This ensures clean bus arbitration and eliminates the need for external bus-hold or direction-control logic in microprocessor interfaces.

DS1265Y-100 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc./Maxim Integrated

Series:: -

Package/Case:: 36-DIP Module (0.610", 15.49mm)

Packaging:: Tube

Product Status:: Obsolete

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: NVSRAM

Technology:: NVSRAM (Non-Volatile SRAM)

Memory Size:: 8Mbit

Memory Organization:: 1M x 8

Memory Interface:: Parallel

Clock Frequency:: -

Write Cycle Time - Word, Page:: 100ns

Access Time:: 100 ns

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 36-EDIP

DS1265Y-100 FAQ

1.How can I place an order for DS1265Y-100 through Aetrix?

Please submit a Request for Quotation (RFQ) for DS1265Y-100 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for DS1265Y-100 reliable?

The price and inventory of DS1265Y-100 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1265Y-100 is usually 5 days.

3.What payment methods are accepted for DS1265Y-100?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1265Y-100 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for DS1265Y-100?

DS1265Y-100 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your DS1265Y-100 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for DS1265Y-100?

For technical support, including DS1265Y-100 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1265Y-100 requirements.

6.How does Aetrix verify that DS1265Y-100 is sourced from the original manufacturer or authorized distributors?

All DS1265Y-100 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1265Y-100 meets industry standards.

7.What is the process for return or replacement of DS1265Y-100?

All DS1265Y-100 units undergo pre-shipment inspection (PSI). If there is an issue with DS1265Y-100, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The DS1265Y-100 part is unused and in its original packaging.

Return procedure for DS1265Y-100:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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