Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Semtech Corporation GN2406-INE3

Name: GN2406-INE3
Brand: Semtech Corporation
SKU: GN2406-INE3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: GN2406-INE3

Manufacturer:: Semtech Corporation

Category:: Application Specific Clock/Timing

Package:: 48-QFN

Datasheet:: GN2406-INE3.pdf

Description:: IC CONDITIONER RE-TIMER

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,044

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

GN2406-INE3 from Gennum is a quad-channel, 10 Gb/s reference-free CDR (Clock and Data Recovery) with integrated limiting amplifier and transmit de-emphasis, supporting data rates from 9.95 to 11.3 Gb/s, >0.7 UI input jitter tolerance, and 400–800 mV differential output voltage, deployed in optical modules and active copper cables for InfiniBand QDR and 40GbE.

For engineers reviewing the GN2406-INE3 datasheet, pinout, applications, or equivalent options, key selection criteria include its reference-free CDR architecture, per-channel independent locking, 28 dB loss compensation via de-emphasis, I²C programmability, and 7×7 mm 48-pin QFN package compatibility with GN2405.

Technical Context

The GN2406-INE3 implements a fully reference-free CDR architecture per channel, enabling autonomous lock without external clock, and supports quarter-rate (2.5 Gb/s) and half-rate (5 Gb/s) modes via automatic rate detection. Its high-sensitivity limiting amplifier front-end eliminates need for discrete limiters in optical receiver paths.

Each channel provides independent re-timer bypass up to 11.3 Gb/s, programmable output swing (400–800 mV), and loss-of-signal detection with adjustable threshold. De-emphasis is applied on transmit outputs to compensate up to 28 dB of channel loss, while input jitter tolerance exceeds 0.7 UI.

Key Specifications

Parameter	Value and Actual Design Meaning
Data Rate Range	9.95–11.3 Gb/s per channel; enables full compliance with 10GbE, InfiniBand QDR, and 40GbE KR4 applications.
Input Jitter Tolerance	>0.7 UI; ensures reliable data recovery under severe inter-symbol interference and crosstalk in backplane or cable channels.
Differential Output Voltage	400–800 mV; programmable swing allows optimization for driver stage loading and signal integrity across varying trace lengths.
De-emphasis Capability	Up to 28 dB loss compensation; mitigates high-frequency attenuation in active copper cables and long PCB traces.
Supply Voltage	Single 3.3 V supply; simplifies power delivery design and reduces BOM count versus dual-rail alternatives.
Package	7×7 mm, 48-pin QFN; surface-mount footprint compatible with automated assembly and thermal management in dense line-card layouts.
Control Interface	I²C serial interface; enables configuration, monitoring, and LOS threshold adjustment without additional control logic or GPIOs.

Pinout & Package

GN2406-INE3 is housed in a 7×7 mm, 48-pin QFN package with exposed thermal pad. Pin functions are defined per channel (IN0P/IN0N through OUT3P/OUT3N), plus dedicated EQ, CDR, and Driver control lines, I²C interface (SCL/SDA), and power/ground terminals.

Pin/Terminal	Circuit Role	Design Meaning
IN0P / IN0N IN1P / IN1N IN2P / IN2N IN3P / IN3N	Differential data inputs (x4 channels)	High-sensitivity limiting amplifier inputs; accept degraded signals down to low amplitude with >0.7 UI jitter tolerance.
OUT0P / OUT0N OUT1P / OUT1N OUT2P / OUT2N OUT3P / OUT3N	Differential data outputs (x4 channels)	Programmable CDR outputs with de-emphasis; deliver clean, retimed signals at 400–800 mV swing for downstream laser drivers or connectors.
SCL / SDA	I²C serial interface	Two-wire bus for configuring CDR lock mode, de-emphasis level, LOS threshold, and channel enable/disable.
VDD / GND (x multiple)	Power and ground	Dedicated pins per quadrant minimize supply noise coupling; thermal pad enhances heat dissipation under 1.2 W typical operation.

Key Features

Feature	Design Value
Reference-free CDR architecture	Eliminates need for external clock source or crystal oscillator, reducing system cost, board space, and timing complexity.
Per-channel independent operation	Enables mixed-rate operation (e.g., one channel at 10.3125 Gb/s, another at 2.5 Gb/s) without cross-talk or synchronization overhead.
Integrated limiting amplifier	Replaces discrete limiting amplifiers in optical module RX paths, improving sensitivity and reducing component count in QSFP/SFP+ designs.
Configurable de-emphasis	Adjustable high-frequency boost compensates frequency-dependent loss in copper cables or FR4 backplanes up to 28 dB.
Automatic rate detection	Identifies 2.5 Gb/s (quarter-rate) and 5 Gb/s (half-rate) modes without host intervention, ensuring backward compatibility.

Applications

Optical Module Receive Path	Active Copper Cable Assembly
Use Scenario: GN2406-INE3 placed after TIA in QSFP+ or SFP+ optical transceivers to recover degraded signals from photodiodes. IC Role / Device Role / Timing Role: Receive-side CDR with limiting amplifier and jitter cleanup; resets timing budget before feeding ASIC or MAC layer. Use Value: Enables use of lower-cost TIAs and longer fiber runs by recovering signals with >0.7 UI jitter and sub-mV input sensitivity.	Use Scenario: Integrated into active twinaxial copper cables for InfiniBand QDR or 40GbE, between host ASIC and remote module. IC Role / Device Role / Timing Role: Retimer with de-emphasis on transmit side and limiting on receive side; restores signal integrity across 3–7 m cable lengths. Use Value: Compensates up to 28 dB loss and suppresses crosstalk-induced jitter, enabling reliable 10 Gb/s per lane over passive copper infrastructure.
10Gb/s Serial Backplane Extension	QSFP Line Card Retimer
Use Scenario: Mounted on midplane or line card to extend reach of 10GbE KR links across 20–40 inch FR4 backplanes. IC Role / Device Role / Timing Role: Bidirectional retiming node; cleans jitter and resets skew budget on both TX and RX paths of 4-lane interfaces. Use Value: Improves bit error rate by >10⁴× versus direct connection, due to low output jitter (<0.3 ps RMS) and robust input tolerance.	Use Scenario: Embedded on switch/router line cards to condition signals between ASIC and pluggable QSFP modules. IC Role / Device Role / Timing Role: Protocol-transparent retimer; operates independently of InfiniBand, Ethernet, or Fibre Channel framing. Use Value: Allows ASIC placement farther from front-panel modules via de-emphasis, relaxing layout constraints and easing thermal management.

Optical Module Receive Path

Active Copper Cable Assembly

Use Scenario: GN2406-INE3 placed after TIA in QSFP+ or SFP+ optical transceivers to recover degraded signals from photodiodes.

IC Role / Device Role / Timing Role: Receive-side CDR with limiting amplifier and jitter cleanup; resets timing budget before feeding ASIC or MAC layer.

Use Value: Enables use of lower-cost TIAs and longer fiber runs by recovering signals with >0.7 UI jitter and sub-mV input sensitivity.

Use Scenario: Integrated into active twinaxial copper cables for InfiniBand QDR or 40GbE, between host ASIC and remote module.

IC Role / Device Role / Timing Role: Retimer with de-emphasis on transmit side and limiting on receive side; restores signal integrity across 3–7 m cable lengths.

Use Value: Compensates up to 28 dB loss and suppresses crosstalk-induced jitter, enabling reliable 10 Gb/s per lane over passive copper infrastructure.

10Gb/s Serial Backplane Extension

QSFP Line Card Retimer

Use Scenario: Mounted on midplane or line card to extend reach of 10GbE KR links across 20–40 inch FR4 backplanes.

IC Role / Device Role / Timing Role: Bidirectional retiming node; cleans jitter and resets skew budget on both TX and RX paths of 4-lane interfaces.

Use Value: Improves bit error rate by >10⁴× versus direct connection, due to low output jitter (<0.3 ps RMS) and robust input tolerance.

Use Scenario: Embedded on switch/router line cards to condition signals between ASIC and pluggable QSFP modules.

IC Role / Device Role / Timing Role: Protocol-transparent retimer; operates independently of InfiniBand, Ethernet, or Fibre Channel framing.

Use Value: Allows ASIC placement farther from front-panel modules via de-emphasis, relaxing layout constraints and easing thermal management.

Equivalent & Alternatives

The following parts are listed as comparable options for similar CDR and signal conditioning applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
GN2405-INE3	Features input equalizer instead of limiting amplifier; optimized for TX-side CDR in modules with pre-compensated traces/connectors.	Used in transmit path where channel loss occurs before the CDR; GN2406-INE3 is preferred for RX-side optical recovery.	Select GN2405-INE3 when equalization is needed upstream of CDR; GN2406-INE3 when high-sensitivity limiting is required downstream of TIA.
MAX3795AETL+	Single-channel 10.3 Gb/s CDR with limiting amp; no de-emphasis; requires external reference clock; 32-pin TQFN.	Limited to single-lane applications; lacks multi-lane integration and reference-free operation of GN2406-INE3.	Choose MAX3795AETL+ only for low-density, clocked systems where quad-channel integration and reference-free operation are not required.

Compared with GN2405-INE3 and MAX3795AETL+, GN2406-INE3 uniquely combines quad-channel reference-free CDR, integrated limiting amplifiers, and programmable de-emphasis in a single 48-pin QFN-enabling compact, low-power, clockless retiming for optical RX and active cable applications where jitter cleanup and loss compensation are co-required.

Availability

GN2406-INE3 is available at Aetrix Electronics and suitable for optical transceiver modules, active copper cable assemblies, and 10Gb/s serial backplane retiming applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for GN2406-INE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Gennum Corporation was a fabless semiconductor company specializing in high-speed analog and mixed-signal ICs for optical communications and data center interconnects before its acquisition by Semtech in 2011.

The GN2406-INE3 belongs to Gennum's CDR and signal conditioning product line, designed specifically for robust, reference-free retiming in optical modules, active cables, and backplane systems operating at 10 Gb/s and beyond.

FAQ

What is the primary function of the GN2406-INE3 in optical module designs?

The GN2406-INE3 serves as a receive-side CDR with integrated limiting amplifier in optical modules. It recovers degraded signals from TIAs, cleans jitter exceeding 0.7 UI, and delivers retimed, de-emphasized outputs to laser drivers or host ASICs-eliminating need for discrete limiters and simplifying RX path design in QSFP+ and SFP+ modules.

Does the GN2406-INE3 require an external reference clock to operate?

No, the GN2406-INE3 uses Gennum's reference-free CDR architecture and does not require any external clock source. It autonomously locks to incoming data streams from 9.95 to 11.3 Gb/s, including quarter-rate (2.5 Gb/s) and half-rate (5 Gb/s) modes, reducing system complexity and BOM cost compared to clocked alternatives.

How many differential channels does the GN2406-INE3 support, and what are their roles?

The GN2406-INE3 supports four fully independent differential channels (IN0P/N through IN3P/N and corresponding OUT0P/N through OUT3P/N). Each channel performs clock and data recovery, limiting amplification on input, and programmable de-emphasis on output-enabling simultaneous retiming of 40GbE KR4 or InfiniBand QDR lanes without shared resources.

What is the maximum channel loss compensation capability of the GN2406-INE3?

The GN2406-INE3 provides transmit de-emphasis capable of compensating up to 28 dB of high-frequency channel loss. This enables reliable operation over long active copper cables (up to 7 m) and FR4 backplanes (up to 40 inches), maintaining signal integrity without requiring external equalization or repeaters.

Is the GN2406-INE3 pin-compatible with any other Gennum devices?

Yes, the GN2406-INE3 is fully pin-compatible with the GN2405-INE3. Both share identical 48-pin QFN packaging, pin assignments, and power/control interface. The key functional difference lies in the front-end: GN2406-INE3 uses limiting amplifiers (optimized for RX), while GN2405-INE3 uses input equalizers (optimized for TX).

GN2406-INE3 Specifications

Product attributes: Attribute value

Manufacturer:: Semtech Corporation

Series:: -

Package/Case:: 48-QFN

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: No

Main Purpose:: InfiniBand, Ethernet

Input:: Clock

Output:: Clock

Number of Circuits:: 1

Ratio - Input:Output:: 4:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: -

Voltage - Supply:: 3.3V

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 48-QFN (7x7)

GN2406-INE3 FAQ

1.How can I place an order for GN2406-INE3 through Aetrix?

Please submit a Request for Quotation (RFQ) for GN2406-INE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for GN2406-INE3 reliable?

The price and inventory of GN2406-INE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for GN2406-INE3 is usually 5 days.

3.What payment methods are accepted for GN2406-INE3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for GN2406-INE3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for GN2406-INE3?

GN2406-INE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your GN2406-INE3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for GN2406-INE3?

For technical support, including GN2406-INE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your GN2406-INE3 requirements.

6.How does Aetrix verify that GN2406-INE3 is sourced from the original manufacturer or authorized distributors?

All GN2406-INE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that GN2406-INE3 meets industry standards.

7.What is the process for return or replacement of GN2406-INE3?

All GN2406-INE3 units undergo pre-shipment inspection (PSI). If there is an issue with GN2406-INE3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The GN2406-INE3 part is unused and in its original packaging.

Return procedure for GN2406-INE3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-11 Comparator Circuit: Voltage Thresholds, Op-Amp Differences, LM393 and Practical Design

Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …