Semtech Corporation GS1559-CB
- Part No.:
- GS1559-CB
- Manufacturer:
- Semtech Corporation
- Category:
- Video Processing
- Package:
- 100-LBGA
- Datasheet:
-
GS1559-CB.pdf
- Description:
- IC VIDEO RECLOCKER 100BGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
GS1559-CB from Gennum is a multi-rate HD-SDI/SD-SDI/DVB-ASI deserializer with integrated reclocker, loop-through cable driver, and parallel 20-bit/10-bit CMOS output. It supports SMPTE 292M (1.485 Gb/s), SMPTE 259M-C (270 Mb/s), and DVB-ASI (270 Mb/s) standards, performs NRZI→NRZ decoding and descrambling, and delivers reclocked or buffered serial loop-through output. It is used in broadcast video receivers for signal integrity restoration and format conversion.
For engineers reviewing the GS1559-CB datasheet, pinout, applications, or equivalent options, this device is selected for SMPTE-compliant video demultiplexing, real-time error correction (CRC, TRS, EDH, ANC), automatic standard detection (HD/SD/DVB-ASI), and low-jitter reclocking in professional broadcast infrastructure.
Technical Context
The GS1559-CB implements dual differential serial inputs (DDI1/DDI2) with 2×1 mux selection, integrated 75 Ω termination, and carrier detect inputs (CD1/CD2). Its reclocker achieves ±0.3 UI input jitter tolerance and supports external VCO control via LF, VCO_VCC, VCO_GND, and VCO pins for precise lock stability across HD/SD rates.
The device operates in Master or Slave mode via MASTER/SLAVE pin: Master mode enables auto-detection of SMPTE 292M/259M-C and DVB-ASI streams with status outputs (SD/HD, RC_BYP, LOCKED); Slave mode allows explicit configuration of data rate, bypass, and protocol via control pins (SD/HD, DVB_ASI, SMPTE_BYPASS).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supported Standards | SMPTE 292M (1.485 Gb/s), SMPTE 259M-C (270 Mb/s), DVB-ASI (270 Mb/s) |
| Input Jitter Tolerance | ±0.3 UI - ensures robust locking to degraded coaxial cable signals in broadcast environments |
| Parallel Output Bus | 20-bit or 10-bit LVCMOS/LVTTL - configurable via 20bit/10bit pin for demuxed luma/chroma or multiplexed Y/C data |
| Output Clock Frequencies | PCLK = 148.5 MHz (HD 10-bit), 74.25 MHz (HD 20-bit), 27 MHz (SD 10-bit), 13.5 MHz (SD 20-bit) |
| Power Supplies | 1.8 V core (CORE_VDD), 3.3 V I/O (IO_VDD), 3.3 V charge pump (CP_VDD) - separates analog/digital domains for noise immunity |
| Error Processing | Detects and corrects CRC, TRS, line number, EDH CRC, and ANC checksum errors - reduces downstream video artifacts |
| Loop-Through Driver | Selectable reclocked or non-reclocked SDO output with mute-on-loss-of-signal and dual slew-rate control |
Pinout & Package
GS1559-CB is housed in an 11 mm × 11 mm Pb-free QFN-100 package with exposed thermal pad. Pin assignments follow Gennum's standardized HD-LINX™ II layout, supporting high-density PCB routing and thermal management in broadcast equipment.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DDI1 / DDI1, DDI2 / DDI2 | Differential Serial Input Pairs | Accept SMPTE or DVB-ASI streams; selectable via IP_SEL; include internal 75 Ω termination |
| SDO | Serial Loop-Through Output | Reclocked or buffered output; supports mute-on-loss-of-signal and adjustable swing for cable drive compliance |
| DOUT[19:0] | Parallel Data Output Bus | 20-bit LVCMOS/LVTTL bus delivering luma/chroma or ancillary data; timing-synchronous to PCLK |
| LOCKED, SD/HD, RC_BYP | Status Outputs (Master Mode) | Indicate lock status, detected data rate (HD/SD), and reclock enable state - simplifies system-level monitoring |
| MASTER/SLAVE, SMPTE_BYPASS, DVB_ASI | Mode Configuration Inputs | Enable auto-detection (Master) or manual protocol/rate selection (Slave) - supports flexible integration |
| FIFO_LD, DATA_ERROR, YANC, CANC | Control & Status Signals | Provide frame-level load pulse, aggregated error flag, and ancillary data presence indicators - enable real-time diagnostics |
Key Features
| Feature | Design Value |
|---|---|
| Auto-standard detection | Identifies SMPTE 292M, 259M-C, or DVB-ASI without host intervention - eliminates firmware polling overhead |
| Integrated flywheel | Enables noise-immune H/V/F timing extraction and switch-line lock handling - critical for stable genlock in live production |
| Programmable error correction | Corrects CRC, TRS, EDH, line number, and ANC checksum errors on-the-fly - preserves video fidelity over long cable runs |
| Configurable parallel output | 20-bit demuxed or 10-bit multiplexed output via 20bit/10bit pin - matches FPGA or ASIC interface requirements |
| JTAG + GSPI host interface | Enables full register read/write access for configuration, diagnostics, and error status retrieval - supports in-system validation |
Applications
| Broadcast Video Receiver | HD-SDI Distribution Amplifier |
|---|---|
|
Use Scenario: Receiving and regenerating HD-SDI signals from long coaxial cable runs in OB vans or studio routers. IC Role / Device Role / Timing Role: Deserializes 1.485 Gb/s SMPTE 292M stream, reclocks jitter, decodes NRZI, and outputs clean 20-bit parallel video with embedded timing (H/V/F). Use Value: Restores signal integrity degraded by cable loss and EMI, enabling reliable downstream processing without frame drops. |
Use Scenario: Splitting and retransmitting HD-SDI feeds to multiple monitors or recorders while preserving signal quality. IC Role / Device Role / Timing Role: Receives one HD-SDI input, provides reclocked loop-through SDO output, and drives parallel bus for local monitoring or metadata extraction. Use Value: Eliminates need for discrete reclocker + driver ICs, reducing BOM count and board area in compact DA modules. |
| SDI-to-DVB-ASI Converter | Professional Video Monitor Interface |
|
Use Scenario: Converting legacy SD-SDI camera feeds to DVB-ASI for satellite uplink or IP transport gateways. IC Role / Device Role / Timing Role: Deserializes 270 Mb/s SMPTE 259M-C, performs 8b/10b encoding, and outputs compliant DVB-ASI stream via SDO. Use Value: Enables interoperability between baseband video infrastructure and broadcast transmission systems without external logic. |
Use Scenario: Feeding real-time video and ancillary data (VANC/HANC) to on-screen display processors in master control rooms. IC Role / Device Role / Timing Role: Extracts YANC/CANC flags and parallel video with line numbers and TRS timing - synchronizes graphics overlay with active video. Use Value: Delivers precise, error-corrected timing and metadata required for accurate frame-accurate graphics insertion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rate SDI deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| GS2971-CB | Successor device with enhanced SMPTE 424M (3 Gb/s) support, lower power, and improved jitter performance; same pinout but requires updated firmware. | Required for new 3G-SDI designs; not backward-compatible for legacy 1.5G/270M-only systems due to tighter timing margins. | Choose GS2971-CB for future-proof 3G-SDI deployments; retain GS1559-CB for cost-sensitive, field-proven 1.5G/SD-SDI systems. |
| LMH0384 | TI device offering integrated cable equalization (up to 100 m), no built-in VCO interface, and fixed 20-bit parallel output - lacks DVB-ASI mode and ANC processing. | Used in simpler SDI receivers where equalization is needed but advanced error correction or multi-protocol flexibility is not required. | Choose LMH0384 when coaxial equalization is primary concern and DVB-ASI or SMPTE 352M payload handling is unnecessary. |
Compared with GS2971-CB and LMH0384, the GS1559-CB uniquely combines SMPTE 292M/259M-C and DVB-ASI protocol support, on-chip error correction, and programmable loop-through driver - making it optimal for legacy broadcast gear requiring multi-standard interoperability and field-replaceable reliability.
Availability
GS1559-CB is available at Aetrix Electronics and suitable for broadcast video receivers, SDI distribution amplifiers, SDI-to-DVB-ASI converters, and professional monitor interfaces requiring stable component supply across extended product lifecycles.
Supply support for GS1559-CB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Gennum Corporation was a Canadian semiconductor company specializing in high-speed serial interface ICs for professional video, broadcast, and communications markets before its acquisition by Semtech in 2012.
The GS1559-CB belongs to Gennum's HD-LINX™ II family, designed specifically for SMPTE-compliant video signal recovery, reclocking, and protocol-aware deserialization in broadcast infrastructure equipment.
FAQ
What video standards does the GS1559-CB support?
The GS1559-CB supports SMPTE 292M (1.485 Gb/s HD-SDI), SMPTE 259M-C (270 Mb/s SD-SDI), and DVB-ASI (270 Mb/s) standards. It performs protocol-specific descrambling, NRZI→NRZ decoding, word alignment, and 8b/10b decoding as required by each standard. The GS1559-CB automatically detects and configures itself for these formats in Master mode or accepts manual selection in Slave mode.
Does the GS1559-CB require an external VCO?
Yes, the GS1559-CB requires an external Voltage Controlled Oscillator such as the GO1555 (recommended for new designs) or GO1525. It provides dedicated pins - VCO, VCO_VCC, VCO_GND, and LF - to interface with the VCO for reclocking. The GS1559-CB generates the control voltage and supplies bias power but does not integrate the oscillator core.
How does the GS1559-CB handle error correction?
The GS1559-CB detects and corrects CRC, TRS, line number, EDH CRC, and ANC checksum errors in real time. Correction is enabled via the IOPROC_EN/DIS pin and individual register controls. Corrected data is inserted into the parallel output stream, and the DATA_ERROR pin aggregates all detectable errors. The GS1559-CB also supports illegal code remapping and optional error reporting via host interface registers.
What is the function of the LOOP-THROUGH cable driver in the GS1559-CB?
The GS1559-CB's loop-through cable driver provides a selectable serial output (SDO) that can be configured as either reclocked (synchronized to internal PLL) or non-reclocked (buffered pass-through). It includes loss-of-signal mute, high-impedance mode, adjustable swing, and automatic slew-rate selection based on HD/SD mode - ensuring compliance with SMPTE cable drive specifications for daisy-chain or distribution applications.
Can the GS1559-CB operate without external configuration?
Yes, in Master mode (MASTER/SLAVE = HIGH), the GS1559-CB performs fully autonomous operation: automatic standard detection, rate identification (HD/SD), reclock enable/disable (RC_BYP), and status signaling (LOCKED, SD/HD). No host processor is required for basic deserialization, though the GSPI/JTAG interface remains available for diagnostics and advanced feature control.
GS1559-CB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Semtech Corporation
- Series:
- HD-LINX® II
- Package/Case:
- 100-LBGA
- Packaging:
- Tray
- Product Status:
- Obsolete
- Function:
- Reclocker
- Applications:
- Professional Video
- Standards:
- SMPTE
- Control Interface:
- Serial
- Voltage - Supply:
- 3V ~ 3.6V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 100-LBGA (11x11)
GS1559-CB FAQ
1.How can I place an order for GS1559-CB through Aetrix?
Please submit a Request for Quotation (RFQ) for GS1559-CB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for GS1559-CB reliable?
The price and inventory of GS1559-CB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for GS1559-CB is usually 5 days.
3.What payment methods are accepted for GS1559-CB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for GS1559-CB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for GS1559-CB?
GS1559-CB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your GS1559-CB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for GS1559-CB?
For technical support, including GS1559-CB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your GS1559-CB requirements.
6.How does Aetrix verify that GS1559-CB is sourced from the original manufacturer or authorized distributors?
All GS1559-CB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that GS1559-CB meets industry standards.
7.What is the process for return or replacement of GS1559-CB?
All GS1559-CB units undergo pre-shipment inspection (PSI). If there is an issue with GS1559-CB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The GS1559-CB part is unused and in its original packaging.
Return procedure for GS1559-CB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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