Semtech Corporation GS1561-CFTE3
- Part No.:
- GS1561-CFTE3
- Manufacturer:
- Semtech Corporation
- Category:
- Video Processing
- Package:
- 80-LQFP
- Datasheet:
-
GS1561-CFTE3.pdf
- Description:
- IC VIDEO DESERIALIZER 80LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
GS1561-CFTE3 from Gennum is a dual-rate SMPTE/DVB-ASI deserializer IC performing NRZI-to-NRZ decoding, 8b/10b decoding, descrambling, and reclocking for HD-SDI (1.485 Gb/s), SD-SDI (270 Mb/s), and DVB-ASI (270 Mb/s) serial digital video interfaces. It delivers 20-bit or 10-bit parallel CMOS output at 148.5 MHz / 74.25 MHz / 27 MHz / 13.5 MHz and supports automatic standards detection, error correction, and ancillary data processing in broadcast infrastructure equipment.
For engineers reviewing the GS1561-CFTE3 datasheet, pinout, applications, or equivalent options, this page provides verified functional identity, confirmed pin roles, validated timing behavior, real-world error-handling capabilities, and direct alternative options for HD/SD video receiver design.
Technical Context
The GS1561-CFTE3 implements a dual-input serial digital interface with 2×1 mux selection between DDI1/DDI1 and DDI2/DDI2 differential inputs, integrated termination, and a wide-tolerance reclocker (±0.3 UI input jitter tolerance). It operates in master or slave mode, with automatic HD/SD rate detection via SD/HD pin control and lock indication via LOCKED output.
In SMPTE mode, it performs SMPTE 259M-C/292M descrambling, word alignment, flywheel-based H/V/F timing extraction, and line-level error correction (CRC, TRS, EDH, ANC). In DVB-ASI mode, it performs 8b/10b decoding, K28.5 sync alignment, and transport packet status signaling - all configurable via GSPI host interface or JTAG test access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Data Rates | 1.485 Gb/s (HD-SDI), 1.485/1.001 Gb/s (HD-SDI), 270 Mb/s (SD-SDI/DVB-ASI) - supports auto-switching between HD and SD rates without reconfiguration |
| Parallel Output Bus | 20-bit or 10-bit CMOS - selectable via 20bit/10bit pin; enables flexible FPGA/ASIC interface depth matching |
| Output Clock Frequencies | 148.5 MHz (HD), 74.25 MHz (HD half-rate), 27 MHz (SD), 13.5 MHz (SD half-rate) - directly synchronized to recovered video timing |
| Input Jitter Tolerance | ±0.3 UI (total 0.6 UI) - ensures robust lock under cable-induced jitter in long-run broadcast installations |
| Standards Compliance | SMPTE 292M, SMPTE 259M-C, DVB-ASI - validated for professional video signal integrity per industry specification |
| Power Supplies | 1.8 V core (PD_VDD, BUFF_VDD), 3.3 V I/O (IO_VDD), 3.3 V charge pump (CP_VDD) - separates analog/digital domains for noise immunity |
| Error Correction Capability | Line-based CRC, TRS, EDH CRC, ANC checksum, and line number correction - corrects detected errors and inserts valid replacement words |
Pinout & Package
GS1561-CFTE3 is housed in an 80-pin LQFP package (12 mm × 12 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Gennum DS27360-12 (June 2009), with dedicated differential inputs, carrier detect signals, parallel data outputs (DOUT[19:0]), timing outputs (H/V/F), and GSPI/JTAG interface pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DDI1 / DDI1, DDI2 / DDI2 | Differential serial input pairs | Accept SMPTE or DVB-ASI streams; selected via IP_SEL; internally terminated |
| CD1 / CD2 | Carrier detect inputs | LVCMOS/LVTTL inputs indicating valid serial signal presence; mute outputs when HIGH |
| DOUT[19:0] | Parallel digital output bus | 20-bit demultiplexed or 10-bit multiplexed video/data payload; synchronous to PCLK |
| H / V / F | Timing signal outputs | Horizontal sync, vertical sync, and field ID outputs derived from internal flywheel; jitter-immune |
| PCLK | Parallel clock output | Recovered pixel clock at 148.5/74.25/27/13.5 MHz - phase-aligned to video data |
| SD/HD | Data rate indicator/control | Output in master mode; input in slave mode - indicates or selects HD (LOW) vs SD (HIGH) operation |
| LOCKED | Reclock lock status | Active-HIGH signal confirming stable PLL lock to incoming serial stream |
| DATA_ERROR | Error flag output | Active-LOW pulse indicating detection of any correctable/uncorrectable error (CRC, TRS, EDH, etc.) |
Key Features
| Feature | Design Value |
|---|---|
| Auto-configurable HD/SD mode | Eliminates manual register programming - device detects and locks to 1.485 Gb/s or 270 Mb/s streams autonomously |
| Integrated flywheel timing extraction | Provides noise-immune H/V/F generation independent of input jitter, enabling stable downstream video processing |
| Full SMPTE 352M payload ID detection | Identifies embedded video standard (e.g., 1080i, 720p, 480i) and data format without external parsing logic |
| Configurable error correction engine | Corrects line-based CRC, TRS, EDH, ANC checksum, and line number errors - inserts valid replacement words into output stream |
| GSPI + JTAG dual-interface control | Enables both production programming (JTAG) and runtime configuration (GSPI) using shared pins with mode-select JTAG/HOST pin |
Applications
| Broadcast HD-SDI Receiver | SD-SDI Distribution Amplifier |
|---|---|
|
Use Scenario: Receiving uncompressed 1080p60 video over coaxial cable in OB vans or studio routers. IC Role / Device Role / Timing Role: Deserializes and reclocks SMPTE 292M-compliant 1.485 Gb/s stream; extracts H/V/F timing; corrects transmission errors. Use Value: Enables bit-accurate reconstruction of high-resolution video with sub-pixel timing stability and real-time error recovery. |
Use Scenario: Splitting and regenerating SD-SDI signals across multiple monitoring paths in post-production suites. IC Role / Device Role / Timing Role: Receives and reclocks SMPTE 259M-C 270 Mb/s input; generates clean parallel output for fanout and re-serialization. Use Value: Restores signal integrity after cable loss, eliminates jitter accumulation, and supports multi-path distribution without degradation. |
| DVB-ASI Transport Stream Decoder | Multi-standard Video Processing Front-End |
|
Use Scenario: Demultiplexing MPEG-TS packets from satellite/cable headend feeds in broadcast encoders. IC Role / Device Role / Timing Role: Performs DVB-ASI 8b/10b decoding and K28.5 word alignment; outputs parallel TS data with asi_sync_det flag. Use Value: Provides deterministic, low-latency transport stream delivery to FPGA-based demux engines with sync-character validation. |
Use Scenario: Unified video acquisition board supporting HD-SDI, SD-SDI, and DVB-ASI inputs in field-deployable equipment. IC Role / Device Role / Timing Role: Single-chip solution for auto-detecting and processing three major broadcast serial formats via shared parallel bus and timing outputs. Use Value: Reduces BOM count and PCB area versus discrete deserializer solutions while maintaining format-specific compliance and error handling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial digital video deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| GS1560A-CFTE3 | Includes integrated serial loop-through cable driver (SDO/SDO); GS1561-CFTE3 lacks SDO pins and RSET/CD_VDD/CD_GND power rails | Required where reclocked or buffered serial output loop-through is needed; not suitable if only deserialization is required | Select GS1560A-CFTE3 only when serial output regeneration is part of system architecture |
| THS8200IPFP | Single-rate (HD-only) deserializer; no DVB-ASI support; no error correction; 10-bit parallel output only | Limited to HD-SDI receive in cost-sensitive non-broadcast applications; lacks SMPTE 259M-C and DVB-ASI compliance | Choose THS8200IPFP only for HD-only, non-critical timing applications without error handling requirements |
Compared with GS1560A-CFTE3, GS1561-CFTE3 removes redundant driver circuitry to reduce power and cost in pure receive-only systems; compared with THS8200IPFP, GS1561-CFTE3 adds dual-rate auto-detection, full error correction, and DVB-ASI capability essential for professional broadcast infrastructure.
Availability
GS1561-CFTE3 is available at Aetrix Electronics and suitable for broadcast video receivers, SDI distribution amplifiers, DVB-ASI transport decoders, and multi-standard video processing front-ends requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for GS1561-CFTE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Gennum Corporation was a Canadian semiconductor company specializing in high-speed serial interface ICs for professional video, broadcast, and communications markets before its acquisition by Semtech in 2012.
The GS1561-CFTE3 belongs to Gennum's HD-LINX® II family, designed specifically for SMPTE and DVB-ASI compliant video deserialization in broadcast infrastructure where signal integrity, timing accuracy, and error resilience are mission-critical.
FAQ
What video standards does the GS1561-CFTE3 support?
The GS1561-CFTE3 supports SMPTE 292M (HD-SDI), SMPTE 259M-C (SD-SDI), and DVB-ASI serial digital interfaces. It auto-detects and locks to 1.485 Gb/s, 1.485/1.001 Gb/s, or 270 Mb/s data rates, and performs format-specific descrambling, decoding, and word alignment accordingly. The GS1561-CFTE3 does not support HDMI, DisplayPort, or non-broadcast protocols.
Does the GS1561-CFTE3 include a built-in cable driver?
No, the GS1561-CFTE3 does not include a serial loop-through cable driver. That functionality is exclusive to the GS1560A-CFTE3 variant. The GS1561-CFTE3 pinout omits SDO/SDO, RSET, CD_VDD, CD_GND, and SDO_EN/DIS pins entirely - confirmed in the official pin assignment table (DS27360-12, p.7). Use GS1561-CFTE3 strictly for deserialization-only applications.
How does the GS1561-CFTE3 handle timing extraction in noisy environments?
The GS1561-CFTE3 uses an internal flywheel circuit for H/V/F timing extraction, providing jitter immunity during periods of input instability or transient loss-of-signal. This flywheel maintains accurate horizontal and vertical synchronization even when the serial input exhibits ±0.3 UI jitter - critical for maintaining frame lock in live broadcast systems. The GS1561-CFTE3 outputs these stabilized timing signals on dedicated H, V, and F pins.
Can the GS1561-CFTE3 correct errors in received video data?
Yes, the GS1561-CFTE3 performs real-time correction of multiple error types including line-based CRC, TRS, EDH CRC, ANC checksum, and line number errors. When enabled via IOPROC_EN/DIS and individual register controls, it inserts corrected words into the parallel output stream. This capability is confirmed in the device's functional description and error correction section (DS27360-12, pp.45–62). The GS1561-CFTE3 does not perform forward error correction (FEC) on transport layers.
What interface options are available to configure the GS1561-CFTE3?
The GS1561-CFTE3 supports two configuration interfaces: a 4-wire GSPI (CS_TMS, SCLK_TCK, SDIN_TDI, SDOUT_TDO) for runtime host control, and IEEE 1149.1 JTAG for boundary scan testing and programming. Mode selection is controlled by the JTAG/HOST pin. Both interfaces share the same physical pins but operate exclusively based on that control signal - no external multiplexing is required. The GS1561-CFTE3 does not support I²C or SPI protocols.
GS1561-CFTE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Semtech Corporation
- Series:
- HD-LINX® II
- Package/Case:
- 80-LQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Deserializer
- Applications:
- Professional Video
- Standards:
- DVB-ASI, SMPTE
- Control Interface:
- Serial
- Voltage - Supply:
- 1.65V ~ 1.95V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 80-LQFP (14x14)
GS1561-CFTE3 FAQ
1.How can I place an order for GS1561-CFTE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for GS1561-CFTE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for GS1561-CFTE3 reliable?
The price and inventory of GS1561-CFTE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for GS1561-CFTE3 is usually 5 days.
3.What payment methods are accepted for GS1561-CFTE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for GS1561-CFTE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for GS1561-CFTE3?
GS1561-CFTE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your GS1561-CFTE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for GS1561-CFTE3?
For technical support, including GS1561-CFTE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your GS1561-CFTE3 requirements.
6.How does Aetrix verify that GS1561-CFTE3 is sourced from the original manufacturer or authorized distributors?
All GS1561-CFTE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that GS1561-CFTE3 meets industry standards.
7.What is the process for return or replacement of GS1561-CFTE3?
All GS1561-CFTE3 units undergo pre-shipment inspection (PSI). If there is an issue with GS1561-CFTE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The GS1561-CFTE3 part is unused and in its original packaging.
Return procedure for GS1561-CFTE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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