Semtech Corporation GS9062-CFE3

Overview

GS9062-CFE3 from Gennum is a dual-standard HD-LINX® II serializer with integrated ClockCleaner™ reclocking, supporting SMPTE 259M-C SD-SDI and DVB-ASI serial digital interfaces. It features 20-bit/10-bit parallel CMOS input, 270 Mb/s serial output, 100 kHz–adjustable PLL loop bandwidth, and internal flywheel-based TRS generation. It serves as the core serialization and jitter-cleaning stage in broadcast video transmission systems.

For engineers reviewing the GS9062-CFE3 datasheet, pinout, applications, or equivalent options, key selection considerations include SMPTE/DVB-ASI mode configuration via DVB_ASI/SMPTE_BYPASS pins, RSET-controlled 800 mV_p-p output swing, 13.5/27 MHz PCLK support, and JTAG/GSPI host interface programmability for EDH, TRS, and SMPTE 352M packet insertion.

Technical Context

The GS9062-CFE3 integrates a fully configurable PLL-based ClockCleaner™ reclocker with user-selectable loop bandwidth down to 100 kHz, enabling >300 ps input jitter tolerance while maintaining SMPTE-compliant output jitter. Its dual-mode architecture supports NRZ-to-NRZI scrambling (SMPTE) or 8b/10b encoding with K28.5 sync word insertion (DVB-ASI), both applied prior to serialization.

Parallel data handling supports 20-bit demultiplexed (13.5 MHz PCLK) or 10-bit multiplexed (27 MHz PCLK) formats, with synchronous control inputs (H/V/F/BLANK) and asynchronous mode-selection pins (DVB_ASI, SMPTE_BYPASS, IOPROC_EN/DIS). All I/O processing - including EDH, TRS, ANC checksum, and illegal code remapping - is optional and enabled via pin strapping or host register writes.

Key Specifications

Pinout & Package

GS9062-CFE3 is housed in an 80-pin LQFP package (12 mm × 12 mm, 0.5 mm pitch) with exposed thermal pad. Power domains are physically separated: CORE_GND/CORE_VDD (digital core), IO_GND/IO_VDD (I/O buffers), CP_GND/CP_VDD (charge pump), PD_GND/PD_VDD (phase detector), CD_GND/CD_VDD (cable driver), and VCO_GND/VCO_VCC (external VCO interface).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serializer applications.

Compared with GS9060-CFE3, the GS9062-CFE3 adds DVB-ASI compatibility, programmable loop bandwidth, and TRS flywheel - enabling broader standard coverage and superior jitter resilience. Versus LMH0384SQ/NOPB, it integrates critical broadcast packet generation, reducing system-level complexity and component count.

Availability

GS9062-CFE3 is available at Aetrix Electronics and suitable for broadcast video transmitters, DVB-ASI transport encoders, multi-standard interface cards, and legacy broadcast equipment upgrades requiring stable component supply and long-term design continuity.

Supply support for GS9062-CFE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Gennum Corporation was a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for professional video, broadcast, and communications infrastructure before its acquisition by Semtech in 2012.

The GS9062-CFE3 belongs to Gennum's HD-LINX® II serializer family, designed specifically for robust, low-jitter serialization of SD video in broadcast environments where SMPTE 259M-C and DVB-ASI interoperability is required.

FAQ

What video standards does the GS9062-CFE3 support?

The GS9062-CFE3 supports SMPTE 259M-C for SD-SDI and DVB-ASI standards natively. In SMPTE mode, it performs NRZ-to-NRZI encoding and scrambling; in DVB-ASI mode, it inserts K28.5 sync words and applies 8b/10b encoding. The GS9062-CFE3 does not support HD-SDI, 3G-SDI, or HDMI protocols.

How is the output swing of the GS9062-CFE3 configured?

The GS9062-CFE3 output swing is set by an external resistor (RSET) connected between the RSET pin and CD_VDD. A 281 Ω ±1% resistor yields a nominal 800 mV_p-p differential output into a 75 Ω load, meeting SMPTE 259M-C amplitude requirements. The GS9062-CFE3 does not support programmable swing via registers - RSET is the sole calibration method.

Does the GS9062-CFE3 require an external VCO?

Yes, the GS9062-CFE3 requires an external voltage-controlled oscillator such as the GO1555 (recommended for new designs) or GO1525. The VCO connects differentially to the VCO/VCO pins, with VCO_VCC and VCO_GND providing isolated power and ground. The GS9062-CFE3 provides the LF control voltage and CP_CAP capacitor interface for PLL loop filtering.

Can the GS9062-CFE3 insert EDH and TRS packets without host processor involvement?

Yes - the GS9062-CFE3 can autonomously generate and insert EDH and TRS packets when IOPROC_EN/DIS is asserted HIGH and corresponding features are enabled via pin strapping or default register states. The internal flywheel locks to embedded TRS or external H/V/F timing, allowing full packet insertion without continuous host intervention. The GS9062-CFE3 retains this capability even during GSPI/JTAG inactivity.

What is the function of the LOCKED pin on the GS9062-CFE3?

LOCKED is a status output that goes HIGH when the GS9062-CFE3 achieves and maintains lock to a valid SMPTE 259M-C or DVB-ASI input stream. It remains LOW during loss-of-lock, invalid input, or reset conditions. This pin provides real-time link integrity feedback to system controllers and is electrically compatible with LVCMOS/LVTTL logic levels. The GS9062-CFE3 asserts LOCKED only after stable PLL lock and valid data framing detection.