Semtech Corporation GS9090ACNE3

Overview

GS9090ACNE3 from Gennum is a 270 Mb/s SMPTE 259M-C and DVB-ASI compliant deserializer with integrated reclocker, line-based FIFO, and NRZI-to-NRZ/8b/10b decoding. It performs descrambling, word alignment, HVF timing extraction, and error detection/correction for broadcast video systems. Delivers 10-bit parallel output at 27 MHz with <145 mW typical power consumption in an 8 mm × 8 mm QFN package.

For engineers reviewing the GS9090ACNE3 datasheet, pinout, applications, or equivalent options, this page provides verified functional context, validated pin roles, confirmed SMPTE/DVB-ASI mode behavior, real-world error handling capabilities (TRS/EDH/ANC), and accurate supply voltage requirements (1.8 V core, 1.8/3.3 V I/O).

Technical Context

The GS9090ACNE3 implements dual-mode operation: in SMPTE 259M-C mode, it performs NRZI-to-NRZ decoding, descrambling, flywheel-based H/V/F timing generation, and SMPTE 352M payload identification; in DVB-ASI mode, it executes 8b/10b decoding, K28.5 sync alignment, and MPEG packet extraction. Both modes use the same internal VCO-based reclocker with wide input jitter tolerance.

Its integrated line-based FIFO supports four user-selectable modes-video delay, clock phase interchange, DVB-ASI packet extraction, and ancillary data extraction-with programmable read clock (RD_CLK) and reset (RD_RESET). The device uses a dual-host interface: GSPI for configuration/status register access and JTAG for boundary scan testing, selected via the JTAG/HOST pin.

Key Specifications

Pinout & Package

GS9090ACNE3 is housed in a 56-pin QFN package (8 mm × 8 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Gennum DS34714 Rev. 7 (May 2010), including dedicated analog power domains (PLL_VDD, VCO_VDD, BUFF_VDD), dual-mode control pins (AUTO/MAN, DVB_ASI, SMPTE_BYPASS), and programmable multi-function outputs (STAT[3:0]).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar deserializer applications.

Compared with GS9090ACNE3, GS9091ACNE3 offers identical form-factor and register compatibility but narrower DVB-ASI bandwidth, while LMH0384SQ/NOPB trades protocol versatility for superior input equalization - making GS9090ACNE3 the only option supporting full SMPTE+DVB-ASI feature set in a single chip.

Availability

GS9090ACNE3 is available at Aetrix Electronics and suitable for broadcast infrastructure, digital video test equipment, and multi-standard media processors requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for GS9090ACNE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Gennum Corporation was a Canadian semiconductor company specializing in high-speed serial interface ICs for professional video, broadcast, and communications markets before its acquisition by Semtech in 2012.

The GS9090ACNE3 belongs to the GenLINX® III family, designed specifically for SMPTE/DVB-ASI deserialization in broadcast-grade equipment where deterministic timing, embedded data handling, and multi-standard interoperability are mandatory.

FAQ

What standards does the GS9090ACNE3 natively support?

The GS9090ACNE3 natively supports SMPTE 259M-C (including NRZI-to-NRZ decoding, descrambling, and flywheel-based timing extraction) and DVB-ASI (8b/10b decoding and K28.5 word alignment). It does not support SMPTE 372M (HD-SDI) or SMPTE 424M (3G-SDI), nor does it implement HDMI, DisplayPort, or USB protocols. All standard-specific functionality is verified in Gennum DS34714 Rev. 7.

Does the GS9090ACNE3 require external loop filter components?

Yes, the GS9090ACNE3 requires external passive components connected to LF+ (pin 56) and LF− (pin 1) to configure the PLL loop filter. These components determine loop bandwidth and stability per the Typical Application Circuit (Part B) in DS34714 Rev. 7. No internal loop filter is provided; omission results in failed lock or unstable reclocking.

How does the GS9090ACNE3 handle ancillary data packets?

The GS9090ACNE3 detects and extracts SMPTE 352M payload identifier packets, identifies received video standard automatically, and supports programmable ANC data detection. Ancillary data checksum errors are detected and corrected when IOPROC_EN is HIGH and enabled via the IOPROC_DISABLE register. Extraction occurs in FIFO Ancillary Data Extraction mode.

Can the GS9090ACNE3 operate without the internal FIFO enabled?

Yes, the GS9090ACNE3 supports FIFO bypass mode when FIFO_EN is LOW. In this mode, parallel data (DOUT[9:0]) is clocked synchronously with PCLK (27 MHz) instead of RD_CLK, eliminating FIFO latency and simplifying timing for basic deserialization. All I/O processing features remain available if IOPROC_EN is HIGH.

What is the function of the STAT[3:0] pins on the GS9090ACNE3?

The STAT[3:0] pins are programmable multi-function outputs configured via the IO_CONFIG register. Each can output H, V, F, FIFO_LD, ANC_DETECT, EDH_DETECT, FIFO_FULL, or FIFO_EMPTY signals. Default behavior depends on FIFO mode and SMPTE/DVB-ASI selection; for example, in SMPTE video mode, STAT[2:0] typically output H/V/F timing signals.