Infineon Technologies IR2135SPBF

Overview

IR2135SPBF from Infineon Technologies is a high-voltage, high-speed 3-phase bridge driver IC with six independent gate drive outputs (three high-side and three low-side), rated for +600V offset voltage, 200 mA/420 mA peak output current, 10–20 V gate supply range, 750 ns/700 ns typical turn-on/turn-off propagation delay, and 250 ns matched deadtime. It integrates an analog current-sense amplifier and over-current shutdown for motor inverter stages.

For engineers reviewing the IR2135SPBF datasheet, IR2135SPBF pinout, IR2135SPBF application, or IR2135SPBF equivalent, key selection criteria include floating channel dV/dt immunity, bootstrap-compatible high-side operation up to 600 V, 2.5 V logic compatibility, integrated current trip feedback, and fault-clear functionality via FLT-CLR pin.

Technical Context

The IR2135SPBF implements three independent half-bridge drivers using proprietary HVIC technology, enabling monolithic high-side floating operation referenced to VS pins with ±50 V/ns dV/dt immunity. Each channel features matched propagation delays (750 ns on / 700 ns off) and programmable deadtime (250 ns typ.) to prevent shoot-through in 3-phase PWM inverters.

It embeds a rail-to-rail operational amplifier (CA+, CA−, CAO) for analog current sensing across an external shunt, with 5–10 V/µs slew rate and 50–70 dB CMRR/PSRR. Fault detection triggers simultaneous shutdown of all six outputs, signaled via open-drain FAULT pin and cleared by active-low FLT-CLR.

Key Specifications

Pinout & Package

IR2135SPBF is housed in a 28-lead SOIC (wide body) package with gull-wing leads, optimized for thermal dissipation and PCB layout in high-power motor drive applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-phase gate driver applications.

Compared with IR2135SPBF, IR2133SPBF offers identical functionality at equal 600 V rating and cost, while IRS2336M trades analog current sensing for integrated bootstrap diodes-making IR2135SPBF optimal where real-time analog current feedback and full 600 V capability are mandatory.

Availability

IR2135SPBF is available at Aetrix Electronics and suitable for industrial motor drives, BLDC controllers, appliance inverters, and UPS systems requiring stable component supply, long-lifecycle support, and traceable sourcing for production programs.

Supply support for IR2135SPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a global semiconductor leader specializing in power management, sensor, and automotive ICs, with deep expertise in high-voltage gate drivers and motor control solutions.

The IR21xx family-including IR2135SPBF-is designed specifically for ruggedized 3-phase inverter applications, emphasizing dV/dt immunity, integrated protection, and analog feedback to simplify high-performance motor drive design.

FAQ

What is the maximum allowable dV/dt at the VS pins?

The IR2135SPBF is rated for ±50 V/ns dV/dt at the VS1–VS3 pins under normal operating conditions. This specification ensures reliable high-side floating operation during fast switching transients in 3-phase inverters, preventing false triggering or latch-up. The HVIC process and internal level-shifting circuitry maintain logic integrity even under aggressive bus voltage slew rates encountered with SiC or fast IGBTs.

Can the CAO output drive an MCU ADC directly?

Yes-the CAO output is rail-to-rail (0–5.4 V), has low output impedance (<100 Ω), and delivers ±10 mA short-circuit current, making it compatible with most 12-bit MCU ADCs without buffering. Its 0–30 mV input offset and 50–70 dB CMRR ensure sub-1% measurement accuracy when paired with a precision shunt resistor and proper PCB layout (guard ring, Kelvin sensing).

How does the deadtime function interact with HIN/LIN inputs?

Deadtime is implemented in hardware between complementary HO/LO outputs: when a LIN signal turns on LO, the corresponding HO remains off for ≥250 ns before responding to HIN; similarly, HO turn-off enforces ≥250 ns delay before LO turn-on. This prevents shoot-through regardless of input timing-no external deadtime insertion or MCU delay is required, simplifying firmware and improving reliability.

Is the FLT-CLR pin synchronous or asynchronous?

The FLT-CLR pin is asynchronous and active-low: asserting it low immediately clears the internal fault latch and restores normal operation once the fault cause (e.g., over-current or UVLO) is removed. No clock or timing relationship with HIN/LIN is required, enabling immediate recovery from transient faults such as startup inrush or line surges without MCU intervention.