Infineon Technologies IR2235JTR

Overview

IR2235JTR from Infineon Technologies is a high-voltage, high-speed 3-phase bridge driver IC with six independent gate drive channels (three high-side and three low-side), rated for up to 1200 V offset voltage, ±420 mA/±200 mA output current, 750 ns/700 ns typical turn-on/turn-off propagation delay, and 250 ns typical deadtime. It integrates an analog current-sense amplifier and over-current shutdown for motor inverter stages in industrial AC drives.

For engineers reviewing the IR2235JTR datasheet, IR2235JTR pinout, IR2235JTR application, or IR2235JTR equivalent, key selection criteria include its 1200 V floating channel capability, matched propagation delays across all six drivers, 2.5 V logic compatibility, integrated current trip function, and fault-clear input with open-drain FAULT output.

Technical Context

The IR2235JTR employs proprietary HVIC technology to enable monolithic high-side floating channel operation up to 1200 V VS offset, with dV/dt immunity and negative transient tolerance. Its independent operational amplifier accepts differential inputs from an external sense resistor and delivers analog current feedback via CAO while supporting over-current shutdown via ITRIP.

All three half-bridge pairs feature matched propagation delays (750 ns ton / 700 ns toff), programmable deadtime (250 ns typ.), and undervoltage lockout on both VCC (9.2–11.6 V threshold) and VB supplies. Logic inputs are CMOS/LSTTL-compatible down to 2.5 V, and outputs are out-of-phase with inputs.

Key Specifications

Pinout & Package

IR2235JTR is housed in a 28-lead SOIC (wide body) package with gull-wing leads, optimized for thermal dissipation and creepage in high-voltage motor control PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-phase high-voltage gate driver applications.

Compared with IR2233JTR and IRS2330MTRPBF, the IR2235JTR uniquely combines 1200 V capability with on-die current amplification and programmable blanking-making it optimal for safety-critical, space-constrained motor control where analog current loop integrity is mandatory.

Availability

IR2235JTR is available at Aetrix Electronics and suitable for industrial AC motor drives, solar PV string inverters, EV auxiliary power systems, and uninterruptible power supplies requiring stable component supply across multi-year production cycles.

Supply support for IR2235JTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs, with leadership in high-voltage gate drivers and silicon carbide solutions.

The IR223x family was designed specifically for ruggedized 3-phase inverter stages in industrial motor drives and renewable energy systems-emphasizing integration, fault resilience, and 1200 V system-level reliability.

FAQ

What is the maximum allowable dV/dt at VS pins for reliable operation?

The IR2235JTR is specified to tolerate ≥50 V/ns transient dV/dt at VS1–VS3 pins without false triggering or latch-up. This rating is validated under worst-case conditions with VB = 15 V and TA = 25°C, enabling use in fast-switching SiC-based inverters where edge rates exceed 30 V/ns. Layout practices-including short, low-inductance VS traces and local decoupling-must be followed to maintain this immunity.

Can the CAO output drive a microcontroller ADC directly?

Yes-CAO delivers a rail-to-rail output (0–5.4 V) with ±20 mV low-level accuracy and 7 mA source capability, compatible with most 12-bit microcontroller ADCs. For optimal SNR, connect CAO to the ADC via a 10 Ω series resistor and 100 nF ceramic capacitor to ground near the MCU pin; avoid sharing the CAO return path with noisy digital grounds.

How does the ITRIP blanking time interact with PWM frequency?

The internal 400 ns ITRIP blanking window begins at each HO/LO edge transition and suppresses false trips caused by switching spikes. At 20 kHz PWM, blanking occupies <0.8% of the period-leaving ample time for valid over-current detection within the same switching cycle. No firmware adjustment is needed; blanking is fully hardware-managed and independent of duty cycle.

Is the FLT-CLR function debounced internally?

No-the FLT-CLR input has no internal debounce; it responds synchronously to logic transitions. A minimum pulse width of 600 ns (per datasheet tfltclr) is required for reliable clearing. To prevent spurious faults in noisy environments, implement RC filtering (e.g., 10 kΩ + 100 pF) or FPGA-based edge detection with ≥1 µs hold time before asserting FLT-CLR.