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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Power Management - Specialized

Infineon Technologies IR3504MTRPBF

Name: IR3504MTRPBF
Brand: Infineon Technologies
SKU: IR3504MTRPBF
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: IR3504MTRPBF

Manufacturer:: Infineon Technologies

Category:: Power Management - Specialized

Package:: 32-VFQFN Exposed Pad

Datasheet:: IR3504MTRPBF.pdf

Description:: IC CTRL XPHASE3 SVID 32-MLPQ

Quantity:: RFQ Add To RFQ list

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Product details

Overview

IR3504MTRPBF from Infineon Technologies is a dual-output AMD SVID control IC for CPU core (VDD) and northbridge auxiliary (VDDNB) power planes, featuring 0.5% system set-point accuracy, 20 MHz error amplifier bandwidth, 10 V/µs slew rate, and programmable dynamic VID slew rates. It coordinates xPHASE3™ phase ICs in high-efficiency, thermally optimized server/desktop CPU VRMs.

For engineers reviewing the IR3504MTRPBF datasheet, IR3504MTRPBF pinout, IR3504MTRPBF application, or IR3504MTRPBF equivalent, key selection criteria include SVID interface compliance, dual independent output control, remote sense differential amplifiers with <50 µA bias, daisy-chain phase timing, and hiccup overcurrent protection with programmable OCSET thresholds.

Technical Context

The IR3504 operates as a master controller in an AMD SVID-compliant multi-phase VRM architecture, managing two independent buck converter outputs via dedicated error amplifiers (EAOUT1/EAOUT2), remote sense inputs (VOSEN1±/VOSEN2±), and analog control buses to phase ICs. It implements boot VID capture from SVC/SVD parallel inputs upon ENABLE assertion.

It integrates a VCCL linear regulator (programmable via VCCLFB), ROSC-based oscillator (250–1500 kHz), CLKOUT/PHSOUT clock distribution, and centralized OVP detection communicated to phase ICs via IIN pins. PG logic deasserts if either VDD or VDDNB deviates >315 mV below respective VDAC reference.

Key Specifications

Parameter	Value and Actual Design Meaning
SVID Interface	AMD-compliant bidirectional serial VID bus with 0.95 V rising threshold and 650 mV falling threshold; enables dynamic voltage programming of both outputs.
Output Accuracy	0.5% overall system set-point accuracy across temperature and load; ensures tight CPU voltage regulation per AMD specification.
Error Amplifier BW	20 MHz unity-gain bandwidth with 10 V/µs slew rate; supports fast transient response for high-di/dt CPU loads.
Switching Frequency	Programmable 250 kHz to 1.5 MHz via ROSC resistor; allows optimization of efficiency, size, and EMI in multi-phase designs.
Remote Sense Bias	<50 µA input bias current on VOSEN+/- inputs; minimizes IR drop error in precision differential sensing at CPU socket.
OVP Detection	Centralized overvoltage detection with ROSC/OVP pin voltage >1.6 V indicating fault; communicates OVP status to phase ICs via IIN pins.
Package	32-lead MLPQ (5 mm × 5 mm, 0.5 mm pitch); thermally enhanced for high-power CPU VRM applications with exposed thermal pad.

Pinout & Package

IR3504MTRPBF uses a 32-lead MLPQ package (5 mm × 5 mm body, 0.5 mm pitch) with exposed thermal pad for efficient heat dissipation in high-current CPU VRMs.

Pin/Terminal	Circuit Role	Design Meaning
1 SVD	SVID Data bidirectional line	Open-drain interface for AMD processor VID communication; requires external pull-up; defines voltage setpoints and mode commands.
2 PWROK	System Power Good input	Enables SVID operation when asserted; tying to VCCL disables SVID and activates VFIX mode using SVC/SVD boot codes.
3 ENABLE	Master enable control	Logic-high enables converter startup and captures 2-bit boot VID from SVC/SVD; floating state is undefined and prohibited.
4 IIN2 / 21 IIN1	Average current monitor inputs	Receive phase-average current signals from VDDNB/VDD phase ICs; also carry OVP fault signals to phase ICs via ISHARE protocol.
11 VOSEN2+ / 12 VOSEN2− / 13 VOSEN1− / 14 VOSEN1+	Differential remote sense inputs	Enable Kelvin sensing at CPU load; reject PCB trace IR drop; require matched routing and <50 µA bias for accuracy.
25 CLKOUT / 26 PHSOUT / 27 PHSIN	Digital phase timing interface	Provide daisy-chained clock distribution (CLKOUT = fsw × #phases; PHSOUT = fsw) without external timing components.
31 PG	Power Good open-collector output	Drives low during startup, fault, or if either VDD/VDDNB falls >315 mV below VDAC; requires external pull-up to VCCL.

Key Features

Feature	Design Value
Dual independent SVID outputs	Separately programmable VDD core and VDDNB auxiliary voltages with independent on/off control and boot VID storage.
Programmable dynamic VID slew	RC networks on VDAC1/VDAC2 pins allow precise control of voltage transition speed to meet AMD di/dt requirements.
Centralized OVP with ISHARE	OVP detection at controller level communicated to all phase ICs via IIN pins-eliminates redundant per-phase OVP circuitry.
VDD output impedance programming	VDRP1 pin buffers IIN1 signal; RC network between VDRP1 and FB1 sets output impedance for load-line compensation.
Hiccup overcurrent protection	OCSET1/OCSET2 pins set constant-current limit thresholds; delay timing programmed via SS/DEL1/SS/DEL2 capacitors.

Applications

Server CPU VRM

Desktop AM4 Platform

Use Scenario: High-current, multi-phase power delivery for AMD EPYC processors requiring strict SVID compliance and dynamic voltage scaling.

IC Role / Device Role / Timing Role: Master SVID controller coordinating up to 8 xPHASE3™ phase ICs; manages VDD/VDDNB sequencing, remote sensing, and PG signaling.

Use Value: Enables compact, high-efficiency VRM design with 0.5% voltage accuracy and daisy-chain timing-reducing BOM count and layout complexity.

Use Scenario: Dual-rail CPU power solution for AMD Ryzen desktop platforms with discrete GPU and memory subsystems.

IC Role / Device Role / Timing Role: Dual-output controller providing independent VDD (core) and VDDNB (I/O die) regulation with boot VID capture and VFIX fallback mode.

Use Value: Supports rapid boot via parallel SVC/SVD VID latching and robust fault handling (PG, hiccup OCP, open-sense detection) for consumer-grade reliability.

Workstation CPU Power

Embedded AMD SoC Systems

Use Scenario: Thermally constrained workstation motherboards powering high-TDP Threadripper CPUs with aggressive transient demands.

IC Role / Device Role / Timing Role: High-bandwidth control IC driving remote-sensed, multi-phase buck converters with 20 MHz error amplifiers and 10 V/µs slew rate.

Use Value: Delivers sub-10 µs transient response and <50 µA remote sense bias-critical for maintaining voltage stability under heavy multi-threaded workloads.

Use Scenario: Space-constrained embedded systems using AMD Ryzen Embedded V1000/U1000 series SoCs with integrated GPU and memory controller.

IC Role / Device Role / Timing Role: Compact 5×5 mm MLPQ controller supporting both VDD and VDDNB rails with simplified PG logic and VCCL bias regulation.

Use Value: Integrates VCCL LDO, clock generation, and phase timing-reducing need for external regulators and timing ICs in fanless designs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output AMD SVID control applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IR35203MTRPBF	Single-output SVID controller with integrated MOSFET drivers; no VDDNB support; higher integration but no dual-rail capability.	Used in simpler single-rail CPU VRMs; lacks auxiliary plane control required for full AMD platform compliance.	Select only if VDDNB rail is omitted or handled separately; not suitable for standard AMD SVID implementations.
MP2940AGQSE-LF-Z	Dual-output SVID controller with PMBus compatibility; includes telemetry reporting (Iout, Vout, Temp); no daisy-chain PHSOUT/PHSIN.	Targets datacenter servers requiring real-time telemetry and PMBus host monitoring-not limited to AMD-specific SVID protocols.	Choose when telemetry and host communication outweigh AMD-specific timing features like daisy-chain phase interleaving.

Compared with IR3504MTRPBF, IR35203MTRPBF reduces component count but sacrifices VDDNB support essential for AMD platforms, while MP2940AGQSE-LF-Z adds telemetry at the cost of losing xPHASE3™-optimized daisy-chain timing-making IR3504 the optimal choice for AMD-compliant, high-density VRMs.

Availability

IR3504MTRPBF is available at Aetrix Electronics and suitable for server CPU VRMs, desktop AM4 motherboards, workstation power modules, and embedded AMD SoC systems requiring stable component supply and long-term industrial availability.

Supply support for IR3504MTRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs, with leadership in high-efficiency DC-DC solutions.

The IR3504 belongs to Infineon's xPHASE3™ controller family, designed specifically for AMD SVID-compliant CPU voltage regulation-emphasizing dual-rail control, remote sensing accuracy, and scalable multi-phase coordination.

FAQ

What is the function of the ROSC/OVP pin?

The ROSC/OVP pin serves dual functions: connecting a resistor to LGND sets the switching frequency (250–1500 kHz) and internal bias currents, while its voltage rises above 1.6 V during overvoltage events to trigger centralized OVP protection and signal phase ICs via the IIN bus. During normal operation, it maintains 0.6 V.

How does the IR3504 handle remote sense line faults?

The IR3504 detects open remote sense lines by monitoring bias current and differential voltage at VOSEN1±/VOSEN2± inputs. If either pair shows excessive offset (>3 mV) or loss of expected bias (<30 µA), the PG output deasserts and the controller halts regulation to prevent incorrect voltage delivery to the CPU.

Can the IR3504 operate without an AMD processor?

Yes-the IR3504 supports VFIX mode: connecting PWROK to VCCL disables SVID and uses SVC/SVD parallel inputs to set fixed 2-bit VID codes for both outputs. This enables standalone bench testing or non-AMD applications where SVID is unavailable.

What is the purpose of the VDRP1 pin?

VDRP1 is a buffered copy of the IIN1 current-sense signal. Connecting an RC network between VDRP1 and FB1 programs the VDD output's effective impedance for load-line compensation-ensuring voltage droop scales correctly with current to maintain CPU stability under dynamic load changes.

IR3504MTRPBF Specifications

Product attributes: Attribute value

Manufacturer:: Infineon Technologies

Series:: XPhase3™

Package/Case:: 32-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Discontinued at Digi-Key

Applications:: Processor

Current - Supply:: 10mA

Voltage - Supply:: 4.75V ~ 7.5V

Operating Temperature:: 0°C ~ 100°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 32-MLPQ (5x5)

IR3504MTRPBF FAQ

1.How can I place an order for IR3504MTRPBF through Aetrix?

Please submit a Request for Quotation (RFQ) for IR3504MTRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for IR3504MTRPBF reliable?

The price and inventory of IR3504MTRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for IR3504MTRPBF is usually 5 days.

3.What payment methods are accepted for IR3504MTRPBF?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for IR3504MTRPBF transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for IR3504MTRPBF?

IR3504MTRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your IR3504MTRPBF order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for IR3504MTRPBF?

For technical support, including IR3504MTRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your IR3504MTRPBF requirements.

6.How does Aetrix verify that IR3504MTRPBF is sourced from the original manufacturer or authorized distributors?

All IR3504MTRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that IR3504MTRPBF meets industry standards.

7.What is the process for return or replacement of IR3504MTRPBF?

All IR3504MTRPBF units undergo pre-shipment inspection (PSI). If there is an issue with IR3504MTRPBF, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The IR3504MTRPBF part is unused and in its original packaging.

Return procedure for IR3504MTRPBF:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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