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Infineon Technologies IR3514MTRPBF
- Part No.:
- IR3514MTRPBF
- Manufacturer:
- Infineon Technologies
- Category:
- Power Management - Specialized
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
IR3514MTRPBF.pdf
- Description:
- IC XPHASE3 CONTROL HYBRD 40-MLPQ
- Quantity:
- Payment:
- Shipping:
Inventory:2,990
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Product details
Overview
IR3514MTRPBF from Infineon Technologies is a dual-output AMD SVID/PVID hybrid control IC for CPU core (VDD) and northbridge auxiliary (VDDNB) power regulation, featuring independent SVI-mode voltage programming, 0.5% system set-point accuracy, 30MHz error amplifier bandwidth, and programmable 250kHz–1.5MHz per-phase switching frequency. It enables compact, high-efficiency VRMs in AMD-based server and desktop platforms.
For engineers reviewing the IR3514MTRPBF datasheet, IR3514MTRPBF pinout, IR3514MTRPBF application, or IR3514MTRPBF equivalent, key selection criteria include SVI/PVI mode configuration via VID1, dual remote-sense capability (VOSEN1±/VOSEN2±), VRRDY assertion logic, PSI_L forwarding for power-state coordination, and ROSC-based oscillator/OCSET current programming.
Technical Context
The IR3514 implements a two-loop, dual-output hybrid controller architecture: one loop for VDD core and another for VDDNB, each with dedicated error amplifiers (EAOUT1/EAOUT2), remote sense inputs (VOSEN1±/VOSEN2±), and current-sense interfaces (IIN1/IIN2). Mode selection (SVI vs. PVI) is latched at ENABLE assertion based on VID1 state.
In SVI mode, it decodes serial VID commands to independently program both output voltages and supports dynamic VID slew rate control via external RC networks on VDAC1/VDAC2; in PVI mode, only VDD is regulated using 6-bit parallel VID while VDDNB is disabled to high-impedance. Over-voltage detection is centralized via ROSC/OVP and communicated to phase ICs through IIN pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Control Interface | AMD Serial VID (SVI) or 6-bit Parallel VID (PVI); mode selected by VID1 at ENABLE assertion |
| Output Accuracy | 0.5% overall system set-point accuracy - ensures tight voltage regulation under load transients and temperature variation |
| Error Amplifier BW | 30 MHz bandwidth with 12 V/µs slew rate - enables fast transient response for CPU dynamic power states |
| Switching Frequency | Programmable 250 kHz to 1.5 MHz per phase via ROSC resistor - allows optimization of size, efficiency, and EMI |
| Remote Sense | Differential Kelvin sensing on VOSEN1± and VOSEN2± with <50 µA bias current - eliminates PCB trace IR drop errors |
| VRRDY Logic | Open-drain output asserted only when both outputs are in regulation (SVI) or VDD only (PVI) - provides reliable VR-ready signaling |
| Oscillator Stability | ROSC pin voltage tightly regulated at 0.600 V ±30 mV - ensures consistent timing for phase interleaving and protection delays |
Pinout & Package
IR3514MTRPBF uses a thermally enhanced 40-lead MLPQ package (6 mm × 6 mm body, 0.5 mm pitch), optimized for high-power CPU VRM applications with exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID1 | Mode Selection Input | Latched at ENABLE to select SVI (VID1=0) or PVI (VID1=1); requires external pull-up |
| PWROK | System Power-Good Input | Enables SVID programming when asserted; ties to VCCL to force VFIX mode |
| IIN1 / IIN2 | Average Current Inputs | Receive per-phase current sum from xPHASE3™ phase ICs; also carry OVP signals to phase ICs |
| VOSEN1± / VOSEN2± | Differential Remote Sense Inputs | Kelvin connections at load; enable accurate regulation despite PCB resistance |
| ROSC/OVP | Oscillator & Over-Voltage Monitor | Resistor sets switching frequency and bias currents; voltage >1.6 V indicates OVP fault |
| VRRDY | VR-Ready Output | Open-drain signal asserted only after both outputs reach regulation - critical for CPU boot sequencing |
Key Features
| Feature | Design Value |
|---|---|
| Dual Independent Output Control | Separate VDD core and VDDNB regulation paths with dedicated FB, EAOUT, and OCSET pins - enables asymmetric multi-rail CPU power delivery |
| Dynamic VID Slew Rate Programming | External RC network on VDAC1/VDAC2 sets voltage transition speed - prevents overshoot during rapid CPU frequency scaling |
| PSI_L Forwarding | Digital PSI_L output drives phase ICs to enter low-power state - synchronizes power savings across all phases |
| Hiccup Over-Current Protection | Programmable delay via SS/DEL1/SS/DEL2 capacitors - avoids nuisance tripping during inrush while ensuring robust fault handling |
| Centralized OVP with Phase Communication | OVP detection at ROSC/OVP pin triggers immediate shutdown and propagates fault signal via IIN pins - eliminates need for per-phase OVP circuitry |
Applications
| Server CPU Power Delivery | Desktop AMD Platform VRM |
|---|---|
Use Scenario: Dual-rail power supply for AMD Opteron or Phenom processors requiring independent VDD core and VDDNB regulation with dynamic VID scaling. IC Role / Device Role / Timing Role: Primary hybrid controller coordinating up to 8 xPHASE3™ phase ICs; manages SVI command decoding, phase timing via CLKOUT/PHSOUT, and VR-ready sequencing. Use Value: Achieves 0.5% voltage accuracy and sub-10 ms startup time while reducing component count versus discrete PWM+DAC solutions. | Use Scenario: High-efficiency 4–6 phase VRM on ATX motherboards supporting AMD AM3/AM3+ CPUs with PVI/SVI mode flexibility. IC Role / Device Role / Timing Role: Central control IC providing VDD regulation, remote sensing, and hiccup OCP; supports both legacy PVI and modern SVI firmware interfaces. Use Value: Enables single-BOM support for multiple CPU generations via VID1-selectable interface mode and programmable OCSET thresholds. |
| Embedded AMD APU Systems | Workstation Multi-Socket Platforms |
Use Scenario: Compact VRM for AMD A-series APUs in space-constrained embedded systems where thermal performance and layout density are critical. IC Role / Device Role / Timing Role: Dual-output controller with integrated VCCL linear regulator and daisy-chain phase timing - eliminates external clock buffers and reduces BOM cost. Use Value: 6×6 mm MLPQ package with exposed thermal pad delivers 30% lower junction-to-board thermal resistance than QFN alternatives. | Use Scenario: Synchronized dual-CPU power delivery in 2-socket workstation boards requiring matched VDD rail timing and coordinated PWROK/VRRDY handshaking. IC Role / Device Role / Timing Role: Master controller managing two independent IR3514 instances (one per CPU) via shared SVI bus and distributed PHSIN/PHSOUT daisy chain. Use Value: Daisy-chain digital phase timing ensures <±2 ns inter-phase skew without external timing components - critical for ripple cancellation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output AMD CPU controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35201MTRPBF | Single-chip solution integrating controller + 2-phase drivers; no external phase ICs required; supports newer SVI2 protocol | Reduces total component count but lacks scalability beyond 2 phases; not compatible with xPHASE3™ architecture | Select for cost-sensitive, low-phase-count designs where integration outweighs expandability |
| UCC7601PW | Analog dual-output controller with fixed 300 kHz frequency; no SVI interface; relies on DACs and discrete comparators for VID | Requires external DACs, level shifters, and protection logic; no PSI_L or daisy-chain timing support | Select only for legacy designs lacking AMD-specific interface requirements or where SVI is unused |
Compared with IR3514MTRPBF, IR35201MTRPBF trades external phase IC flexibility for higher integration and SVI2 compliance, while UCC7601PW offers analog simplicity at the cost of missing AMD-specific features like VRRDY sequencing and remote sense bias optimization.
Availability
IR3514MTRPBF is available at Aetrix Electronics and suitable for server CPU power delivery, desktop AMD platform VRMs, and embedded APU systems requiring stable component supply, long-lifecycle support, and validated thermal performance in 6×6 mm MLPQ packaging.
Supply support for IR3514MTRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs, with leadership in high-efficiency DC-DC conversion and CPU VRM solutions.
The IR35xx family was designed specifically for AMD processor power delivery, addressing the need for scalable, digitally enhanced hybrid controllers that bridge legacy PVI and modern SVI protocols while maintaining analog control loop precision.
FAQ
What determines SVI vs. PVI mode selection on the IR3514MTRPBF?
SVI or PVI mode is determined solely by the logic state of the VID1 pin sampled at the rising edge of the ENABLE signal. If VID1 is low (≤0.85 V) when ENABLE goes high, SVI mode activates; if VID1 is high (≥1.05 V), PVI mode engages. This latching behavior is hardwired and cannot be changed dynamically during operation.
How does the IR3514MTRPBF handle over-voltage protection during dynamic VID transitions?
The IR3514MTRPBF disables OVP detection during dynamic VID down transitions to prevent false triggering caused by intentional undershoot. OVP remains active during power-up, steady-state operation, and VID up-transitions. Detection occurs centrally at the ROSC/OVP pin and is communicated to phase ICs via the IIN pins.
Can the IR3514MTRPBF operate without external phase ICs?
No. The IR3514MTRPBF is a controller-only device and requires external xPHASE3™ phase ICs (e.g., IR3507) to drive high-side/lower-side MOSFETs. It provides gate drive timing, current sensing, and protection logic but contains no integrated power switches or drivers.
What is the function of the VCCL pin and how is its voltage regulated?
The VCCL pin supplies power to internal clock circuitry and is regulated by an integrated linear regulator. Its output voltage (typically 5 V) is set by a resistor divider between VCCL and VCCLFB; VCCLDRV provides an error amplifier output to drive an external pass transistor for higher-current VCCL loads, enabling flexible bias rail design.
IR3514MTRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Series:
- XPhase3™
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Processor
- Current - Supply:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-MLPQ (6x6)
IR3514MTRPBF FAQ
1.How can I place an order for IR3514MTRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for IR3514MTRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for IR3514MTRPBF reliable?
The price and inventory of IR3514MTRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for IR3514MTRPBF is usually 5 days.
3.What payment methods are accepted for IR3514MTRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for IR3514MTRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for IR3514MTRPBF?
IR3514MTRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your IR3514MTRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for IR3514MTRPBF?
For technical support, including IR3514MTRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your IR3514MTRPBF requirements.
6.How does Aetrix verify that IR3514MTRPBF is sourced from the original manufacturer or authorized distributors?
All IR3514MTRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that IR3514MTRPBF meets industry standards.
7.What is the process for return or replacement of IR3514MTRPBF?
All IR3514MTRPBF units undergo pre-shipment inspection (PSI). If there is an issue with IR3514MTRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The IR3514MTRPBF part is unused and in its original packaging.
Return procedure for IR3514MTRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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