Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

STMicroelectronics LD39115J33R

Name: LD39115J33R
Brand: STMicroelectronics
SKU: LD39115J33R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: LD39115J33R

Manufacturer:: STMicroelectronics

Category:: Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Package:: 4-UFBGA, FCBGA

Datasheet:: LD39115J33R.pdf

Description:: IC REG LIN 3.3V 150MA 4FLIPCHIP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,482

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

LD39115J33R from STMicroelectronics is a 150 mA ultra-low-noise, low-quiescent-current LDO voltage regulator delivering fixed 3.3 V output with ±2.0 % accuracy at 25 °C, 80 mV typical dropout at 100 mA, 33 µV_RMS noise (1–100 kHz), and logic-controlled shutdown. It operates from 1.5–5.5 V input and supports ceramic output capacitors as small as 1 µF - ideal for powering RF sections and precision analog circuitry in portable battery-powered devices.

For engineers reviewing the LD39115J33R datasheet, LD39115J33R pinout, LD39115J33R application, or LD39115J33R equivalent, key selection criteria include its sub-1 µA shutdown current, thermal/short-circuit protection, flip-chip 4-bump package compatibility with high-density PCB layouts, and stable operation across –40 °C to 125 °C junction temperature.

Technical Context

The LD39115J33R employs a bandgap-referenced error amplifier with internal trimming (1.22 V reference) and PMOS pass transistor architecture to achieve ultra-low dropout and minimal load/line regulation drift. Its enable input controls an internal NMOS switch that disconnects bias circuitry in shutdown mode, reducing total current to ≤1 µA.

Stability is ensured with ≥1 µF ceramic C_OUT and no external compensation required; ESR sensitivity is minimized via internal pole-zero cancellation. Power supply rejection reaches 74 dB at 1 kHz but rolls off above 10 kHz due to bandwidth-limited error amplifier response.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Voltage	Fixed 3.3 V ±2.0 % at 25 °C - ensures reliable logic-level compliance for 3.3 V I/O domains
Max Output Current	150 mA guaranteed - sufficient for powering microcontroller cores, sensors, or RF transceivers
Dropout Voltage	80 mV typ. at 100 mA - enables operation down to VIN = 3.38 V, extending battery runtime in single-cell Li-ion systems
Quiescent Current	20 µA typ. at no load - minimizes standby power loss in always-on subsystems
Output Noise	33 µV_RMS (1–100 kHz) - low enough for noise-sensitive ADC references and PLL VCO supplies
PSRR	74 dB @ 1 kHz - suppresses switching noise from upstream DC-DC converters feeding the LDO
Operating Temp	–40 °C to 125 °C junction - qualified for automotive cabin and industrial edge-node environments
Shutdown Current	≤1 µA max - enables deep-sleep modes without compromising system wake-up latency

Pinout & Package

LD39115J33R uses a flip-chip 4-bump package (0.8 × 0.8 mm, 0.4 mm pitch) with bottom-side terminations - optimized for thermal performance and space-constrained layouts. No exposed pad; soldering requires controlled reflow profile per ST's ECOPACK guidelines.

Pin/Terminal	Circuit Role	Design Meaning
A2 (EN)	Enable logic input	Active-high control: VIH ≥ 0.9 V (VIN), VIL ≤ 0.4 V - compatible with 1.8 V/3.3 V GPIO without level shifters
A1 (GND)	Power ground	Common return path for input/output currents and internal bias - must be low-inductance connection to PCB ground plane
B2 (IN)	Input voltage supply	Accepts 1.5–5.5 V DC; requires local 1 µF ceramic decoupling within 2 mm of pin
B1 (OUT)	Regulated output	Delivers stable 3.3 V; supports 1–22 µF ceramic output capacitance with ESR < 2 Ω for stability

Key Features

Feature	Design Value
Ultra-low noise output	33 µV_RMS (1–100 kHz) - eliminates need for additional LC filtering in sensitive analog rails
Logic-controlled shutdown	EN pin reduces total current to ≤1 µA - enables precise power gating in multi-rail systems
Ceramic capacitor compatibility	Stable with 1 µF C_OUT - avoids cost/size penalties of tantalum or electrolytic capacitors
Internal protection	Thermal shutdown (160 °C) + constant-current short-circuit limiting - prevents damage during fault conditions without external components
Wide input range	1.5–5.5 V operation - supports direct regulation from single Li-ion, NiMH, or USB sources

Applications

Wireless Sensor Node Power

Low-Power MCU Core Supply

Use Scenario: Powering BLE/Wi-Fi SoCs and MEMS sensors in battery-operated IoT endpoints.

IC Role / Device Role / Timing Role: Primary 3.3 V rail regulator providing clean, low-noise supply to RF transceiver and sensor interface circuits.

Use Value: 33 µV_RMS noise and 74 dB PSRR prevent RF desensitization and ADC quantization errors during wireless transmission.

Use Scenario: Supplying core voltage to ARM Cortex-M0+/M3 microcontrollers in portable medical devices.

IC Role / Device Role / Timing Role: Main system LDO delivering regulated 3.3 V to CPU, flash, and peripherals during active and sleep states.

Use Value: 20 µA quiescent current extends battery life in multi-year deployments; 80 mV dropout preserves runtime as battery discharges below 3.5 V.

Industrial HMI Display Backlight

Automotive Infotainment Audio Codec

Use Scenario: Biasing LED drivers and touch controller ICs in ruggedized human-machine interface panels.

IC Role / Device Role / Timing Role: Secondary LDO generating stable 3.3 V for display interface logic and capacitive touch sensing circuitry.

Use Value: –40 °C to 125 °C operating range ensures reliability in uncontrolled ambient environments; EN pin enables synchronized backlight power sequencing.

Use Scenario: Supplying low-noise analog supply to audio DACs and op-amps in vehicle infotainment head units.

IC Role / Device Role / Timing Role: Dedicated LDO isolating sensitive audio circuitry from noisy 5 V main rail generated by buck converters.

Use Value: 33 µV_RMS noise meets THD+N < –95 dB requirements; thermal protection prevents latch-up during transient overloads.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Torex XC6210B332MR-G	300 mA output, 150 mV dropout at 100 mA, 45 µV_RMS noise, SOT-25 package	Higher current capability but larger footprint and higher noise - suitable where load margin >150 mA is needed	Select when board layout allows SOT-25 and system requires >150 mA with moderate noise tolerance
Richtek RT9013-33GB	250 mA output, 250 mV dropout at 150 mA, 40 µV_RMS noise, SOT-23-5 package	Higher dropout and larger package than LD39115J33R - less efficient in low-VIN scenarios	Choose only if existing design uses SOT-23-5 footprint and 250 mV dropout is acceptable

Compared with XC6210B332MR-G and RT9013-33GB, LD39115J33R offers superior noise performance and smallest form factor (0.8×0.8 mm flip-chip), making it optimal for space-constrained, ultra-low-noise applications where 150 mA is sufficient.

Availability

LD39115J33R is available at Aetrix Electronics and suitable for wireless sensor nodes, portable medical devices, industrial HMIs, and automotive infotainment systems requiring stable component supply with full traceability and long-term lifecycle support.

Supply support for LD39115J33R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LD39115J series belongs to ST's ultra-low-noise LDO portfolio targeting battery-powered portable electronics; it was engineered specifically to replace legacy regulators in space- and power-constrained designs without sacrificing noise or thermal performance.

FAQ

What is the minimum input voltage required for LD39115J33R to maintain regulation?

The LD39115J33R requires VIN ≥ VOUT + VDROP to sustain regulation. With a nominal 3.3 V output and 80 mV typical dropout at 100 mA, the minimum functional input is 3.38 V. Absolute minimum VIN is 1.5 V per datasheet, but regulation fails below ~3.38 V under 100 mA load. The UVLO threshold is 1.45 V, below which the device disables output.

Can LD39115J33R be used with a 10 µF ceramic output capacitor?

Yes - the LD39115J33R is stable with ceramic capacitors ranging from 1 µF to 22 µF, as confirmed in Table 5 of the datasheet. A 10 µF X7R ceramic capacitor improves transient response and further reduces output impedance compared to the minimum 1 µF, with no risk of oscillation if ESR remains below 2 Ω at 100 kHz.

Does LD39115J33R require an input capacitor?

While not strictly mandatory for stability, ST recommends a 1 µF ceramic capacitor placed within 2 mm of the IN pin to suppress high-frequency noise and limit peak input current during load transients. Omitting C_IN may degrade PSRR above 1 MHz and increase susceptibility to supply-line ringing, especially when fed from switching regulators.

How does the enable pin behave during power-up sequences?

The EN pin has hysteresis: turn-on occurs when VEN exceeds 1.48 V (typ.), and turn-off occurs at 1.35 V (typ.). During slow-rising VIN, the device remains disabled until both VIN exceeds UVLO (1.45 V) and EN is actively driven high. This prevents partial regulation and ensures clean power sequencing in multi-rail systems.

LD39115J33R Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 4-UFBGA, FCBGA

Packaging:: Tape & Reel (TR)

Product Status:: Active

Output Configuration:: Positive

Output Type:: Fixed

Number of Regulators:: 1

Voltage - Input (Max):: 5.5V

Voltage - Output (Min/Fixed):: 3.3V

Voltage - Output (Max):: -

Voltage Dropout (Max):: 0.11V @ 100mA

Current - Output:: 150mA

Current - Quiescent (Iq):: 50 µA

Current - Supply (Max):: 70 µA

PSRR:: 74dB ~ 67dB (1kHz ~ 10kHz)

Control Features:: Enable

Protection Features:: Over Current, Over Temperature

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 4-FlipChip (0.79x0.79)

LD39115J33R FAQ

1.How can I place an order for LD39115J33R through Aetrix?

Please submit a Request for Quotation (RFQ) for LD39115J33R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LD39115J33R reliable?

The price and inventory of LD39115J33R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD39115J33R is usually 5 days.

3.What payment methods are accepted for LD39115J33R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD39115J33R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LD39115J33R?

LD39115J33R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LD39115J33R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LD39115J33R?

For technical support, including LD39115J33R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD39115J33R requirements.

6.How does Aetrix verify that LD39115J33R is sourced from the original manufacturer or authorized distributors?

All LD39115J33R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD39115J33R meets industry standards.

7.What is the process for return or replacement of LD39115J33R?

All LD39115J33R units undergo pre-shipment inspection (PSI). If there is an issue with LD39115J33R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LD39115J33R part is unused and in its original packaging.

Return procedure for LD39115J33R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-11 Comparator Circuit: Voltage Thresholds, Op-Amp Differences, LM393 and Practical Design

Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …