STMicroelectronics LDLN015PU30R

Overview

LDLN015PU30R from STMicroelectronics is a 150 mA ultra-low-noise linear voltage regulator with fixed 3.0 V output, 6.3 µV_RMS noise (10 Hz–100 kHz), 86 mV typical dropout at 150 mA, and ±1% output accuracy at 25 °C. It operates from 2.1–5.5 V input, supports ceramic output capacitors as low as 0.47 µF, and features logic-controlled enable for <2 µA shutdown current - deployed in noise-sensitive analog signal chains.

For engineers reviewing the LDLN015PU30R datasheet, LDLN015PU30R pinout, LDLN015PU30R application, or LDLN015PU30R equivalent, key selection criteria include ultra-low noise performance, PSRR >90 dB at 1 kHz, thermal/short-circuit protection, DFN6 (2×2 mm) package compatibility, and operation across –40 °C to 125 °C junction temperature.

Technical Context

The LDLN015PU30R implements a high-PSRR, low-quiescent-current LDO architecture optimized for analog power integrity. Its internal bandgap reference and error amplifier deliver ±1% output tolerance over load (1–150 mA), line (2.1–5.5 V), and temperature (–40 to 125 °C), with no external bypass capacitor required.

Enable control uses TTL-compatible thresholds (VEN < 0.4 V = OFF, VEN > 0.9 V = ON), achieving <2 µA off-state current. Thermal shutdown activates at 166 °C with 10 °C hysteresis, and short-circuit current is internally limited to ~300 mA.

Key Specifications

Pinout & Package

LDLN015PU30R is housed in a thermally enhanced DFN6 (2 × 2 mm) package with exposed pad electrically connected to GND. The package supports reflow soldering per JEDEC J-STD-020 and provides R_thJA = 105 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6216D302MR-G and ADP125ARHZ-3.0-R7, the LDLN015PU30R delivers the lowest noise (6.3 µV_RMS) in the smallest footprint (DFN6), making it optimal for space-constrained, noise-critical analog subsystems where 150 mA suffices.

Availability

LDLN015PU30R is available at Aetrix Electronics and suitable for mobile RF front-end power, precision ADC reference supply, and wearable sensor hub core supply requiring stable component supply across automotive-grade temperature ranges and long-lifecycle programs.

Supply support for LDLN015PU30R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LDLN015 series belongs to ST's ultra-low-noise LDO portfolio, engineered specifically for powering noise-sensitive analog circuits in battery-operated and RF-integrated systems.

FAQ

What is the minimum input voltage required for stable 3.0 V output at 150 mA?

The LDLN015PU30R requires VIN ≥ 3.086 V (3.0 V + 86 mV dropout) for full 150 mA output. Below this, regulation fails and VOUT drops linearly with VIN. At light loads (<10 mA), dropout falls to ~40 mV, allowing operation down to 3.04 V.

Can the device operate with a 0.22 µF ceramic output capacitor?

No - ST specifies stability only with COUT ≥ 0.33 µF and ≤ 4.7 µF ceramic capacitors (Table 5 footnote). A 0.22 µF capacitor falls outside the validated stability region and may cause oscillation or poor transient response.

Is the exposed thermal pad internally connected, and how should it be routed?

Yes, the exposed pad is electrically connected to GND. It must be soldered to a dedicated PCB copper pour tied directly to the main GND plane using ≥4 thermal vias (0.3 mm diameter) to ensure R_thJA ≤ 105 °C/W and prevent thermal shutdown under 150 mA load.

Does the enable pin require a pull-up resistor for reliable startup?

No - the EN pin has no internal pull-up. To guarantee startup, an external pull-up to VIN (≥0.9 V) is required unless driven actively high by a processor GPIO. Leaving EN floating risks undefined state and potential failure to enable.