STMicroelectronics LDLN015PU33R

Overview

LDLN015PU33R from STMicroelectronics is an ultra-low-noise, high-PSRR linear voltage regulator delivering a fixed 3.3 V output at up to 150 mA, with 6.3 µV_RMS noise (10 Hz–100 kHz), 86 mV typical dropout at full load, and ±1% output accuracy at 25 °C. It operates from 2.1 V to 5.5 V input, features logic-controlled enable, and targets noise-sensitive analog circuitry in portable electronics.

For engineers reviewing the LDLN015PU33R datasheet, LDLN015PU33R pinout, LDLN015PU33R application, or LDLN015PU33R equivalent, key selection criteria include output noise floor, PSRR above 90 dB at 1 kHz, ceramic-capacitor stability (0.47 µF min), shutdown current <2 µA, and DFN6 (2 × 2 mm) thermal performance (R_thJA = 105 °C/W).

Technical Context

The LDLN015PU33R employs a low-noise bandgap reference and precision error amplifier to maintain tight DC regulation under varying load and line conditions. Its internal architecture integrates thermal shutdown (166 °C trip), short-circuit current limiting (~300 mA), and logic-level enable with hysteresis for reliable power sequencing.

PSRR exceeds 90 dB below 1 kHz and remains >50 dB up to 100 kHz, enabling effective suppression of switching regulator ripple. The device achieves stability without a bypass capacitor and supports fast turn-on (110 µs) while maintaining sub-µA off-state current - critical for battery-backed systems requiring long standby life.

Key Specifications

Pinout & Package

LDLN015PU33R is housed in a thermally enhanced DFN6 package (2 mm × 2 mm, 0.6 mm height) with exposed pad electrically connected to GND for improved thermal dissipation and EMI performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B332MR-G and ADP125ARHZ-3.3-R7, LDLN015PU33R delivers the lowest noise (6.3 µV_RMS) and highest PSRR (92 dB @ 1 kHz) in its class, making it uniquely suitable for RF biasing and precision analog reference applications where spectral purity is non-negotiable.

Availability

LDLN015PU33R is available at Aetrix Electronics and suitable for mobile RF front-end power, portable ADC reference supply, and wearable sensor node core supply requiring stable component supply across production lifecycles.

Supply support for LDLN015PU33R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets.

The LDLN015 series belongs to ST's ultra-low-noise LDO portfolio, engineered specifically for powering noise-sensitive analog and RF circuitry in battery-constrained portable devices.

FAQ

What is the minimum output capacitor required for stability?

The LDLN015PU33R is stable with a minimum 0.47 µF ceramic capacitor on the output, as verified in ST's datasheet Figure 15 (Stability Area). No bypass capacitor is needed, and the device supports up to 4.7 µF for improved transient response. Using smaller values may cause oscillation, while larger values do not degrade stability but increase startup time.

Does the exposed thermal pad require solder connection?

Yes - the exposed pad on the DFN6 package is electrically connected to GND and must be soldered to a dedicated PCB thermal pad tied to the main ground plane. This connection is essential for achieving the specified R_thJA of 105 °C/W and preventing thermal shutdown under 150 mA continuous load.

How does PSRR vary with output current and frequency?

PSRR remains ≥90 dB below 1 kHz at 10 mA load, drops to 89 dB at 10 kHz, and falls to 50 dB at 100 kHz. At higher loads (150 mA), PSRR decreases by ~3 dB across all frequencies due to increased loop gain compression. These values are measured per Table 5 in the datasheet with V_OUT = 1.0 V; performance at 3.3 V is comparable.

Can LDLN015PU33R be used with input voltages below 2.1 V?

No - the absolute minimum operating input voltage is 2.1 V, as specified in Table 5. Operation below this level risks loss of regulation, increased dropout, or undefined behavior. For sub-2.1 V inputs, consider ST's LDLN025 series (1.8 V min. VIN) or alternative low-VIN LDOs with verified performance down to 1.7 V.