STMicroelectronics LDLN025PU25R
- Part No.:
- LDLN025PU25R
- Manufacturer:
- STMicroelectronics
- Package:
- 4-XDFN Exposed Pad
- Datasheet:
-
LDLN025PU25R.pdf
- Description:
- IC REG LINEAR 2.5V 250MA 4DFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,859
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Product details
Overview
LDLN025PU25R from STMicroelectronics is a 250 mA ultra-low-noise low-dropout regulator with 2.5 V fixed output, 6.5 µVRMS output noise, 250 mV dropout at full load, and operation across 1.5–5.5 V input range. It delivers high PSRR (80 dB @ 100 Hz), ±2% output accuracy over line/load/temperature, and logic-controlled shutdown for battery-powered image sensors and RF modules.
For engineers reviewing the LDLN025PU25R datasheet, LDLN025PU25R pinout, LDLN025PU25R application, or LDLN025PU25R equivalent, this LDO is selected for noise-sensitive analog rails in mobile imaging, VCO power, instrumentation front-ends, and precision ADC supplies where quiescent current (12 µA no-load) and stability with 1 µF ceramic capacitors are critical.
Technical Context
The LDLN025PU25R employs a bandgap-referenced PMOS pass transistor architecture enabling ultra-low dropout and controlled quiescent current during dropout-critical for extending runtime in single-cell Li-ion and coin-cell systems. Its internal soft-start and output discharge feature prevent voltage overshoot and ensure clean power sequencing.
Designed for RF and high-resolution analog signal chains, it achieves 80 dB PSRR at 100 Hz and maintains >60 dB up to 100 kHz while delivering 6.5 µVRMS integrated noise (10 Hz–100 kHz) at 250 mA load-validated across –40 °C to +125 °C junction temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output voltage | Fixed 2.5 V ±2% over line, load, and temperature (–40 °C to +125 °C) |
| Max output current | 250 mA continuous; internally current-limited with thermal foldback |
| Dropout voltage | 250 mV at 250 mA (DFN4-1x1 package); enables operation down to 2.75 V input for 2.5 V rail |
| Output noise | 6.5 µVRMS (10 Hz–100 kHz, 250 mA load); suitable for VCO bias and ADC reference supplies |
| PSRR | 80 dB @ 100 Hz, 60 dB @ 100 kHz; suppresses switching noise from upstream DC-DC converters |
| Quiescent current | 12 µA at no-load; rises to 250 µA at 250 mA-optimized for long standby in always-on sensors |
| Enable threshold | VIH = 1.2 V min; VIL = 0.4 V max; compatible with 1.8 V / 3.3 V logic without level shifters |
| Shutdown current | <1 µA (typ. 0.2 µA); enables deep-sleep mode in portable devices |
Pinout & Package
LDLN025PU25R is packaged in DFN4-1x1 (1.0 mm × 1.0 mm, 0.38 mm height, 0.65 mm pitch), featuring an exposed thermal pad that must be soldered to PCB ground for optimal thermal performance (RthJA = 220 °C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Input supply voltage | Accepts 1.5–5.5 V; requires ≥0.7 µF ceramic input capacitor (X7R) for stability |
| VOUT | Regulated output | Delivers 2.5 V ±2%; stable with 0.7–10 µF ceramic output capacitor (ESR 5–500 mΩ) |
| GND | Ground reference | Common return for VIN, VOUT, EN; must connect exposed pad to GND plane |
| EN | Enable control input | Active-high logic; internal 1 MΩ pull-down; drives device into sub-1 µA shutdown when low |
| NC | No-connect terminal | Not internally connected; may be tied to GND for mechanical reinforcement or left floating |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low output noise | 6.5 µVRMS (10 Hz–100 kHz, 250 mA) enables direct powering of RF VCOs and high-SNR ADCs |
| Controlled IQ in dropout | Maintains <250 µA quiescent current even when VIN approaches VOUT-preserves battery life during brownout |
| Output discharge | 230 Ω internal discharge path activates on EN low-prevents residual voltage hold-up on sensitive loads |
| Thermal & short-circuit protection | 160 °C thermal shutdown with 20 °C hysteresis; limits fault current to 250–500 mA |
| Logic-compatible enable | VIH = 1.2 V min supports direct interface with 1.8 V microcontrollers and baseband ICs |
Applications
| Smartphone Image Sensor Power | VCO Bias Supply |
|---|---|
Use Scenario: Powers CMOS image sensor analog core (PLL, ADC, analog front-end) in compact mobile cameras. IC Role / Device Role / Timing Role: Ultra-clean 2.5 V LDO providing isolated, low-noise bias for pixel readout and timing circuits. Use Value: 6.5 µVRMS noise and 80 dB PSRR suppress switching artifacts from SoC DC-DC converters, reducing image fixed-pattern noise. |
Use Scenario: Supplies voltage-controlled oscillator in LTE/Wi-Fi RF transceivers requiring phase stability. IC Role / Device Role / Timing Role: Low-noise, low-drift 2.5 V source for VCO tuning voltage and buffer stages. Use Value: Sub-0.01% load regulation and <250 mV dropout ensure consistent VCO gain and minimal phase jitter under dynamic load. |
| Portable Instrumentation Front-End | Low-Power ADC Reference Rail |
Use Scenario: Powers op-amp and filter stages in handheld multimeters and medical sensors. IC Role / Device Role / Timing Role: Precision 2.5 V supply for signal conditioning chain with tight DC accuracy and transient response. Use Value: ±2% output accuracy over –40 °C to +125 °C and 40 mV load transient recovery support reliable measurement integrity. |
Use Scenario: Supplies reference voltage input (REF+) of 16-bit SAR ADCs in battery-operated data loggers. IC Role / Device Role / Timing Role: Clean, stable 2.5 V reference rail decoupled from noisy digital domains. Use Value: 10 µVRMS noise (1 mA) and 0.002 %/mA static load regulation minimize ADC quantization error and INL drift. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-noise LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B252MR-G | 250 mA, 2.5 V fixed, 12 µVRMS noise, 300 mV dropout @ 250 mA, SOT-25 package | Higher noise and dropout; lacks output discharge and thermal hysteresis | Lower cost for non-RF applications where 12 µVRMS noise is acceptable |
| Analog Devices ADP160AUJZ-2.5-R7 | 150 mA, 2.5 V fixed, 25 µVRMS noise, 195 mV dropout @ 150 mA, TSOT-5 package | Lower current rating; higher noise; no enable pin or output discharge | Suitable only for sub-150 mA loads where board space is constrained and noise <25 µVRMS suffices |
Compared with XC6210B252MR-G and ADP160AUJZ-2.5-R7, LDLN025PU25R uniquely combines 250 mA capability, 6.5 µVRMS noise, output discharge, and thermal hysteresis in a 1 mm² DFN-making it the only option qualified for high-performance mobile RF and imaging rails.
Availability
LDLN025PU25R is available at Aetrix Electronics and suitable for smartphone camera modules, RF transceiver power management, portable instrumentation, and industrial sensor nodes requiring stable component supply with full traceability and extended lifecycle support.
Supply support for LDLN025PU25R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.
The LDLN025 series belongs to ST's ultra-low-noise LDO portfolio, engineered specifically for noise-sensitive analog and RF subsystems in battery-powered portable electronics where PSRR, dropout, and quiescent current are co-optimized.
FAQ
What is the minimum input voltage required for LDLN025PU25R to regulate at 2.5 V?
The minimum input voltage is determined by dropout: at 250 mA load, dropout is 250 mV (DFN4-1x1), so VIN must be ≥2.75 V. At lighter loads, dropout drops to 50 mV (100 mA), allowing VIN as low as 2.55 V. The absolute minimum operating VIN is 1.5 V, but regulation is only guaranteed above VOUT + dropout voltage.
Can LDLN025PU25R be used with tantalum or aluminum electrolytic output capacitors?
No-LDLN025PU25R is optimized for ceramic capacitors (X7R, X5R) with ESR between 5 mΩ and 500 mΩ. Tantalum and aluminum electrolytics typically exhibit ESR >500 mΩ and capacitance drift with temperature/voltage, risking instability and poor transient response per Figure 19's stability region.
Does the NC pin require PCB routing or grounding?
The NC pin (Pin 4 in DFN4-1x1) is not internally connected and has no electrical function. It may be left unconnected or tied to GND for mechanical anchoring-no routing or signal integrity impact. ST's recommended footprint (Figure 34) shows it as a non-plated via or open pad.
How does the output discharge feature behave during enable toggling?
When EN transitions low, the internal 230 Ω discharge path connects VOUT to GND, discharging external output capacitance within microseconds. Discharge stops immediately upon EN high transition. This prevents residual voltage from interfering with downstream logic reset or causing latch-up in adjacent circuitry.
LDLN025PU25R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 4-XDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.5V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 250mA
- Current - Output:
- 250mA
- Current - Quiescent (Iq):
- 25 µA
- Current - Supply (Max):
- 425 µA
- PSRR:
- 80dB ~ 60dB (100Hz ~ 100KHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Short Circuit, Soft Start
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 4-DFN (1x1)
LDLN025PU25R FAQ
1.How can I place an order for LDLN025PU25R through Aetrix?
Please submit a Request for Quotation (RFQ) for LDLN025PU25R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LDLN025PU25R reliable?
The price and inventory of LDLN025PU25R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LDLN025PU25R is usually 5 days.
3.What payment methods are accepted for LDLN025PU25R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LDLN025PU25R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LDLN025PU25R?
LDLN025PU25R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LDLN025PU25R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LDLN025PU25R?
For technical support, including LDLN025PU25R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LDLN025PU25R requirements.
6.How does Aetrix verify that LDLN025PU25R is sourced from the original manufacturer or authorized distributors?
All LDLN025PU25R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LDLN025PU25R meets industry standards.
7.What is the process for return or replacement of LDLN025PU25R?
All LDLN025PU25R units undergo pre-shipment inspection (PSI). If there is an issue with LDLN025PU25R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LDLN025PU25R part is unused and in its original packaging.
Return procedure for LDLN025PU25R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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