STMicroelectronics LDLN025PU29R
- Part No.:
- LDLN025PU29R
- Manufacturer:
- STMicroelectronics
- Package:
- 4-XDFN Exposed Pad
- Datasheet:
-
LDLN025PU29R.pdf
- Description:
- IC REG LINEAR 2.9V 250MA 4DFN
- Quantity:
- Payment:

- Shipping:

Inventory:869
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Product details
Overview
LDLN025PU29R from STMicroelectronics is a 250 mA ultra-low-noise low-dropout (LDO) voltage regulator with 2.9 V fixed output, operating from 1.5 V to 5.5 V input. It delivers 6.5 µVRMS output noise, 80 dB PSRR at 100 Hz, and 250 mV dropout at full load in DFN4-1x1 package-designed for powering noise-sensitive RF modules and image sensors in mobile devices.
For engineers reviewing the LDLN025PU29R datasheet, LDLN025PU29R pinout, LDLN025PU29R application, or LDLN025PU29R equivalent, this LDO offers verified performance in battery-powered instrumentation, VCO biasing, ADC reference supplies, and high-PSRR post-regulation where quiescent current below 12 µA and output discharge capability are critical selection criteria.
Technical Context
The LDLN025PU29R uses a bandgap-referenced error amplifier and PMOS pass transistor to maintain tight output regulation across line, load, and temperature (±2% accuracy). Its controlled quiescent current architecture sustains sub-25 µA IQ even in dropout, extending runtime in deep-sleep states.
Internal soft-start limits inrush current; logic-controlled EN pin enables shutdown with <1 µA total current; output discharge path (230 Ω) actively pulls VOUT to GND when disabled. Thermal and short-circuit protections operate autonomously without external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output voltage | Fixed 2.9 V ±2% over -40 °C to +125 °C, 1 mA–250 mA load, and 1.5 V–5.5 V input |
| Dropout voltage | 250 mV at 250 mA (DFN4-1x1), enabling operation down to VIN = 3.15 V while sustaining regulated 2.9 V |
| Output noise | 6.5 µVRMS (10 Hz–100 kHz, 250 mA load), suitable for VCOs and high-resolution ADCs |
| PSRR | 80 dB @ 100 Hz, 60 dB @ 100 kHz-rejects switching noise from upstream DC/DC converters |
| Quiescent current | 12 µA at no-load; remains ≤425 µA at 250 mA and full temperature range |
| Enable threshold | VIH = 1.2 V, VIL = 0.4 V-compatible with 1.8 V and 3.3 V logic systems |
| Thermal protection | Activates at 160 °C junction temperature with 20 °C hysteresis for reliable fault recovery |
Pinout & Package
LDLN025PU29R is packaged in DFN4-1x1 (1.0 mm × 1.0 mm × 0.38 mm), featuring an exposed thermal pad that must be soldered to PCB GND for optimal thermal performance (RthJA = 220 °C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Input supply connection | Accepts 1.5–5.5 V; requires ≥0.7 µF ceramic input capacitor close to pin |
| VOUT | Regulated output | Delivers stable 2.9 V; supports 0.7–10 µF ceramic output capacitor with ESR 5–500 mΩ |
| GND | Power ground reference | Common return for VIN, VOUT, EN, and exposed pad; must be low-impedance plane |
| EN | Logic-enable control input | Pulled down internally (1 MΩ); drives high (>1.2 V) to enable, low (<0.4 V) to shut down |
| NC | No-connect terminal | Not internally connected; may be tied to GND for mechanical stability or left floating |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low noise regulation | 6.5 µVRMS output noise enables clean power for RF synthesizers and precision analog front-ends |
| Controlled dropout IQ | Quiescent current stays ≤425 µA at 250 mA load and full temperature range-no efficiency collapse in dropout |
| Output discharge | 230 Ω internal FET discharges VOUT to GND within microseconds after EN deactivation-prevents floating bias |
| Stability with ceramics | Guaranteed stable with 0.7–10 µF X7R/X5R ceramic capacitors-eliminates need for tantalum or electrolytic |
| Logic-compatible enable | VIH/VIL thresholds support direct interfacing with 1.8 V, 2.5 V, and 3.3 V microcontrollers |
Applications
| Smartphone RF Front-End | High-Speed Image Sensor Bias |
|---|---|
Use Scenario: Powering VCO and PLL circuitry in LTE/Wi-Fi transceivers where supply ripple induces phase noise. IC Role / Device Role / Timing Role: Ultra-low-noise post-regulator supplying clean 2.9 V bias to VCO core and fractional-N synthesizer. Use Value: 6.5 µVRMS noise and 80 dB PSRR at 100 Hz reduce integrated phase jitter by >30% versus standard LDOs. |
Use Scenario: Providing analog supply to CMOS image sensor pixel arrays during high-frame-rate capture. IC Role / Device Role / Timing Role: Low-noise, fast-transient LDO delivering stable 2.9 V to sensor analog rail with <40 mV load-step deviation. Use Value: 10 µs load transient response and 250 mV dropout allow operation from shared 3.3 V DC/DC rail without headroom penalty. |
| Portable Instrumentation ADC Reference | IoT Wireless Node Subsystem |
Use Scenario: Supplying reference voltage circuitry for 16-bit SAR ADCs in handheld multimeters and data loggers. IC Role / Device Role / Timing Role: Precision LDO generating quiet 2.9 V reference rail decoupled from noisy digital subsystems. Use Value: ±2% output accuracy over temperature and 0.007 %/mA load regulation ensure <0.5 LSB gain error across operating range. |
Use Scenario: Powering BLE/Wi-Fi SoC RF and sensor interface blocks in battery-operated edge nodes. IC Role / Device Role / Timing Role: Enable-controlled LDO providing 2.9 V to RF section only during active transmit/receive bursts. Use Value: 12 µA no-load IQ and <1 µA shutdown current extend 10-year coin-cell lifetime in periodic wake-up applications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-noise LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B292MR-G | 2.9 V fixed, 200 mA, 12 µVRMS noise, no output discharge, SOT-25 package | Lacks output discharge and thermal shutdown; lower PSRR (70 dB @ 100 Hz) | Choose if board space allows SOT-25 and discharge function is unnecessary |
| Analog Devices ADM7172ACPZ-2.9-R7 | 2.9 V fixed, 2 A, 3.2 µVRMS, 120 dB PSRR @ 100 Hz, 10-lead LFCSP | Higher cost, larger footprint, over-specified current capacity for 250 mA use cases | Choose only if >1 A output or sub-4 µVRMS noise is required; not drop-in compatible |
Compared with XC6210B292MR-G, LDLN025PU29R adds output discharge and superior thermal protection; versus ADM7172ACPZ-2.9-R7, it delivers optimized size, cost, and quiescent current for portable 250 mA loads without over-engineering.
Availability
LDLN025PU29R is available at Aetrix Electronics and suitable for smartphone RF modules, image sensor bias rails, portable instrumentation ADC references, and IoT wireless node subsystems requiring stable component supply with guaranteed long-term manufacturability.
Supply support for LDLN025PU29R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, analog, MEMS, and microcontrollers for automotive, industrial, and consumer markets.
The LDLN025 series belongs to ST's ultra-low-noise LDO product line, engineered specifically for noise-critical analog and RF subsystems in battery-constrained portable electronics where PSRR, dropout, and standby current are co-optimized.
FAQ
What is the minimum input voltage required for LDLN025PU29R to maintain regulation at 250 mA?
The minimum input voltage is calculated as VOUT + VDROP = 2.9 V + 0.25 V = 3.15 V under worst-case conditions (DFN4-1x1 package, -40 °C to +125 °C). At room temperature, typical dropout is 120 mV, allowing regulation down to 3.02 V. Input must remain ≥1.5 V per absolute rating, but regulation ceases below 3.15 V at full load.
Can LDLN025PU29R be used with a 1 µF ceramic output capacitor?
Yes-1 µF X7R/X5R ceramic is explicitly validated in the datasheet (Table 5) and falls within the stable region shown in Figure 19. The device requires no ESR tuning and remains stable with ESR as low as 5 mΩ. A 1 µF capacitor meets both minimum (0.7 µF) and recommended (1 µF) values for optimal transient response and noise filtering.
Does the NC pin on LDLN025PU29R require PCB connection?
No-the NC pin is not internally connected and has no electrical function. Per Table 1 and Figure 2, it may be left unconnected or tied to GND for mechanical reinforcement or thermal relief; neither choice affects regulation, noise, or enable behavior. Do not route signals or supply lines to this pin.
How does the output discharge feature operate during shutdown?
When EN is pulled low (<0.4 V), an internal 230 Ω NMOS switch connects VOUT to GND, discharging external output capacitance. This occurs within microseconds (Figure 29), preventing residual voltage from interfering with downstream logic sequencing or causing latch-up in powered-down sections of the system.
LDLN025PU29R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 4-XDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.9V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 250mA
- Current - Output:
- 250mA
- Current - Quiescent (Iq):
- 25 µA
- Current - Supply (Max):
- 425 µA
- PSRR:
- 80dB ~ 60dB (100Hz ~ 100KHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Short Circuit, Soft Start
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 4-DFN (1x1)
LDLN025PU29R FAQ
1.How can I place an order for LDLN025PU29R through Aetrix?
Please submit a Request for Quotation (RFQ) for LDLN025PU29R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LDLN025PU29R reliable?
The price and inventory of LDLN025PU29R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LDLN025PU29R is usually 5 days.
3.What payment methods are accepted for LDLN025PU29R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LDLN025PU29R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LDLN025PU29R?
LDLN025PU29R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LDLN025PU29R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LDLN025PU29R?
For technical support, including LDLN025PU29R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LDLN025PU29R requirements.
6.How does Aetrix verify that LDLN025PU29R is sourced from the original manufacturer or authorized distributors?
All LDLN025PU29R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LDLN025PU29R meets industry standards.
7.What is the process for return or replacement of LDLN025PU29R?
All LDLN025PU29R units undergo pre-shipment inspection (PSI). If there is an issue with LDLN025PU29R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LDLN025PU29R part is unused and in its original packaging.
Return procedure for LDLN025PU29R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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