STMicroelectronics M95040-RMC6TG

Overview

M95040-RMC6TG from STMicroelectronics is a 4-Kbit (512-byte) serial SPI bus EEPROM with 1.8 V to 5.5 V single-supply operation, 20 MHz max clock frequency, and integrated ECC for single-bit error correction. It features a dedicated 16-byte identification page with permanent lock capability, quarter/half/whole-array write protection, and operates across –40 °C to +85 °C - deployed in industrial control modules for parameter storage and firmware revision tracking.

For engineers reviewing the M95040-RMC6TG datasheet, M95040-RMC6TG pinout, M95040-RMC6TG application, or M95040-RMC6TG equivalent, key selection criteria include supply voltage range compatibility (1.8–5.5 V), identification page lockability, ECC-enabled read reliability, and SO8N/ECOPACK2 packaging for space-constrained PCB layouts.

Technical Context

This device implements a standard SPI interface with CPOL=0/CPHA=0 or CPOL=1/CPHA=1 mode support, where data is latched on the rising edge of C and output on the falling edge. The internal architecture includes an HV generator and sequencer for EEPROM programming, a status register with WIP/WEL/BP1/BP0 bits, and transparent ECC x1 logic applied per memory byte.

It supports byte- and page-write operations (≤5 ms), offers hardware-assisted block protection via BP1/BP0 bits controlling 0–100% of the 512-byte array, and integrates a power-on-reset circuit that ensures WEL=0 and WIP=0 at startup - eliminating spurious writes during power ramp-up.

Key Specifications

Pinout & Package

Supplied in RoHS-compliant, halogen-free SO8N (ECOPACK2, 150 mil width) package with standard 8-pin DIP footprint and gull-wing leads.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial SPI EEPROM applications.

Compared with AT25DF041A-SSH-T and M950040-DWDG, M95040-RMC6TG uniquely balances 1.8 V compatibility, ECC reliability, and SO8N manufacturability - making it optimal for cost-sensitive, safety-aware industrial nodes where parameter integrity and supply flexibility are non-negotiable.

Availability

M95040-RMC6TG is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, automotive body control modules, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for M95040-RMC6TG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and non-volatile memory solutions for industrial, automotive, and consumer markets.

The M950x0 series targets robust, low-voltage serial EEPROM applications demanding high endurance, long data retention, and secure parameter storage - especially where SPI interface simplicity and proven reliability are critical.

FAQ

What is the purpose of the identification page in M95040-RMC6TG?

The identification page is a dedicated 16-byte memory region used to store immutable device-specific data such as serial numbers, MAC addresses, or cryptographic keys. Once locked via the LID instruction, it becomes permanently read-only - preventing modification even by subsequent WRSR or WRITE commands. This feature is exclusive to M95040-DF variants and is confirmed in DS1639 Rev 14 Section 6 Instructions.

Does M95040-RMC6TG support 1.8 V operation with full timing specifications?

Yes - the "-R" suffix denotes 1.8 V to 5.5 V operation, and all AC/DC parameters including 20 MHz max clock, 5 ms write time, and –40 °C to +85 °C operation are fully specified at 1.8 V per DS1639 Rev 14 Tables 8–10 and 17. No derating or reduced performance is required at minimum supply.

How does the HOLD pin behave during an active write cycle?

The HOLD pin cannot suspend an ongoing internal write cycle (tW); it only pauses SPI communication before or between instructions. During tW, the WIP bit remains set and Q stays high-impedance. If HOLD is asserted mid-transaction, the device ignores further clocks until HOLD is deasserted and S remains low - but the write continues uninterrupted per DS1639 Section 5.2.

Can the block protection bits (BP1/BP0) be changed after the identification page is locked?

Yes - BP1/BP0 reside in the non-volatile status register and are modified via WRSR independently of the identification page lock state. Locking the ID page (LID) only affects the 16-byte ID region; BP bits continue to control write access to the main 512-byte array as defined in Table 2 of DS1639 Rev 14.