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STMicroelectronics M95256-RDW6TP
- Part No.:
- M95256-RDW6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95256-RDW6TP.pdf
- Description:
- IC EEPROM 256KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:282
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Product details
Overview
M95256-RDW6TP from STMicroelectronics is a 256-Kbit serial SPI EEPROM organized as 32,768 × 8 bits, operating from 1.8 V to 5.5 V supply, featuring 64-byte page write (≤5 ms), 4M+ write cycles, and 200-year data retention. It integrates an identification page with permanent lock capability and supports dual SPI modes (CPOL/CPHA = 0/0 or 1/1) for microcontroller interfacing in embedded control and sensor calibration systems.
For engineers reviewing the M95256-RDW6TP datasheet, M95256-RDW6TP pinout, M95256-RDW6TP application, or M95256-RDW6TP equivalent, key selection criteria include its 1.8 V minimum VCC, WLCSP8 footprint (1.289 × 1.376 mm), hardware/software write protection granularity (quarter/half/whole array), and identification page locking via LID instruction - all critical for secure firmware parameter storage in space-constrained IoT nodes.
Technical Context
The device implements a full SPI interface with dedicated HOLD and WRITE PROTECT pins enabling real-time transaction suspension and configurable memory lockdown. Its status register (SRWD, BP1/BP0, WEL, WIP) provides non-volatile block protection control and write-in-progress visibility without halting host communication.
It features dual-mode SPI compatibility (CPOL=0/CPHA=0 and CPOL=1/CPHA=1), ensuring interoperability with diverse MCU peripherals. The identification page (64 bytes) is accessible only via RDID/WRID instructions and supports irreversible read-only locking via the LID command - a hardware-enforced security layer absent in standard SPI EEPROMs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32 Kbytes), organized as 32768 × 8 bits - sufficient for bootloader config, calibration coefficients, and device identity storage in resource-limited edge nodes. |
| Supply voltage | 1.8 V to 5.5 V - enables direct interface with 1.8 V logic (e.g., ARM Cortex-M0+/M33) and legacy 3.3/5 V systems without level-shifting. |
| Write time | ≤5 ms per byte or per 64-byte page - allows rapid field updates of sensor offset tables or runtime configuration without blocking host CPU for extended periods. |
| Data retention | >200 years at +25 °C - guarantees long-term integrity of factory-programmed identifiers and calibration data across product lifecycle. |
| Endurance | >4 million write cycles - supports frequent logging or counter updates in industrial monitoring applications. |
| Operating temp | −40 °C to +85 °C - qualified for automotive cabin modules, industrial PLC I/O modules, and outdoor smart metering. |
| SPI clock max | 20 MHz - enables sub-16 µs per byte transfer, reducing firmware update latency in high-throughput telemetry systems. |
Pinout & Package
Package: WLCSP8 (1.289 × 1.376 mm), ECOPACK2-compliant, bottom-side bump layout optimized for ultra-compact PCB footprints in wearables and medical patches.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S (Chip Select) | Active-low device enable | Edge-sensitive + level-sensitive input; requires falling edge after power-up before first instruction - prevents spurious writes during voltage ramp. |
| D (Data In) | SPI serial input | Latches data/instructions on rising C edge; accepts WREN, WRITE, WRSR, and LID commands - primary path for configuration and data loading. |
| C (Clock) | SPI serial clock | Supports CPOL/CPHA = (0,0) or (1,1); output Q changes on falling edge - ensures deterministic timing alignment with MCU SPI peripheral. |
| Q (Data Out) | SPI serial output | Drives MSB-first read data (memory array, status register, ID page) on falling C edge - enables reliable high-speed readback without additional strobes. |
| VCC | Power supply | 1.8–5.5 V input with internal POR; requires local 10–100 nF decoupling - accommodates battery-backed or wide-input DC-DC rails. |
| VSS | Ground reference | Common return for all signals and VCC - must be low-impedance connection to avoid noise-induced status register corruption. |
| HOLD | Communication pause | Halts ongoing SPI transfer without deselecting device or resetting state - preserves address pointer and WEL bit during host interrupt servicing. |
| W (Write Protect) | Hardware lock control | Combined with SRWD bit to freeze BP1/BP0 settings - prevents accidental overwrite of protected memory blocks even if WREN is asserted. |
Key Features
| Feature | Design Value |
|---|---|
| Identification page (64 bytes) | Dedicated non-volatile area for device-specific parameters (e.g., serial number, calibration constants), permanently lockable via LID instruction - eliminates need for external secure storage. |
| Flexible write protection | Configurable via Status register (BP1/BP0) to protect quarter/half/entire array, plus hardware lock via W pin - enables layered security for boot code vs. user data regions. |
| Dual SPI mode support | Native compatibility with both (CPOL, CPHA) = (0,0) and (1,1) - removes requirement for MCU SPI mode reconfiguration when sharing bus with other peripherals. |
| High endurance & retention | 4 million write cycles and 200-year data retention at +25 °C - validated for lifetime logging in unattended infrastructure sensors (e.g., water/gas meters). |
| Low-voltage operation | 1.8 V minimum VCC - enables direct integration with energy-harvesting PMUs and coin-cell-powered BLE modules without voltage boosting. |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
|
Use Scenario: Storing temperature/pressure sensor offset and gain coefficients post-factory calibration, updated only during maintenance. IC Role / Device Role / Timing Role: Non-volatile parameter repository with hardware-locked ID page holding unique sensor serial and calibration date. Use Value: Eliminates recalibration drift by preserving factory-trimmed values across 10+ years of field operation, verified under −40 °C to +85 °C thermal cycling. |
Use Scenario: Holding FDA-mandated device configuration profiles (e.g., infusion pump flow rates, ECG lead settings) with tamper-proof audit trail. IC Role / Device Role / Timing Role: Secure configuration store where ID page is locked at manufacturing to prevent runtime modification of safety-critical parameters. Use Value: Meets IEC 62304 software safety requirements via hardware-enforced read-only lock, avoiding firmware-level vulnerability to malicious reprogramming. |
| Automotive Body Control Module | Smart Wearable Personalization |
|
Use Scenario: Retaining seat/mirror position memory, lighting presets, and door lock behavior across ignition cycles in 12 V vehicle electrical systems. IC Role / Device Role / Timing Role: Low-power EEPROM interfaced directly to 3.3 V MCU GPIOs, leveraging HOLD to suspend writes during CAN bus arbitration delays. Use Value: Survives repeated cold cranking (down to 6 V) due to 1.8 V operational floor and built-in POR - ensures no loss of user preferences after battery disconnect. |
Use Scenario: Storing biometric profile templates (heart rate variability baselines, activity thresholds) in compact earbuds or fitness bands. IC Role / Device Role / Timing Role: Ultra-small WLCSP8 EEPROM co-located with BLE SoC, using 20 MHz SPI to minimize flash programming time during OTA updates. Use Value: 1.289 × 1.376 mm footprint saves >0.8 mm² vs. TSSOP8, enabling thinner form factors while maintaining 4M-cycle endurance for daily sync operations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25SF041-SSHD-B | 4 Mbit capacity, quad SPI interface, 1.7–2.0 V min VCC, no identification page | Higher density for firmware patch storage; lacks hardware-lockable ID page and dual-SPI mode flexibility | Select when >256 Kbit memory is required and quad I/O bandwidth justifies added MCU driver complexity. |
| BR24G256FJ-3GE2 | I²C interface, 2.5–5.5 V supply, 1 Mbit, no HOLD pin, 100 kcycles endurance | Lower pin count (5-pin SOP-J8), but incompatible with SPI buses and unsuitable for high-write-frequency logging | Choose only for cost-sensitive, low-update-rate applications where I²C is already dominant and 100 kcycle endurance suffices. |
Compared with AT25SF041-SSHD-B and BR24G256FJ-3GE2, M95256-RDW6TP uniquely balances ultra-compact WLCSP8 packaging, 1.8 V operation, dual-SPI compatibility, and hardware-enforced ID page locking - making it optimal for secure, space-constrained, mixed-voltage embedded systems requiring guaranteed parameter integrity.
Availability
M95256-RDW6TP is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, automotive body control modules, and smart wearable personalization requiring stable component supply across multi-year production cycles.
Supply support for M95256-RDW6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, MEMS, and non-volatile memory solutions for industrial, automotive, and consumer markets.
M95256-RDW6TP belongs to ST's serial EEPROM product line, engineered specifically for secure, low-voltage, high-reliability data storage in space-constrained embedded systems - emphasizing robustness against voltage transients, extended data retention, and hardware-assisted memory protection.
FAQ
What is the function of the HOLD pin on M95256-RDW6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When driven low while Chip Select (S) is active, it places Serial Data Output (Q) in high-impedance and ignores Serial Clock (C) and Data Input (D). This allows the host MCU to service interrupts or perform other tasks while preserving the current transaction context - essential for real-time systems with tight latency budgets.
How does the identification page differ from the main memory array?
The identification page is a dedicated 64-byte region accessible only via RDID/WRID instructions, separate from the main 32 Kbyte array. Unlike main memory, it supports irreversible locking via the LID instruction - once locked, its contents become permanently read-only, preventing overwrite even if Write Enable (WREN) is asserted. This makes it ideal for storing immutable device identity or calibration metadata.
Can M95256-RDW6TP operate reliably at 1.8 V with full 20 MHz SPI speed?
Yes - the M95256-R variant (including M95256-RDW6TP) is fully specified for 1.8 V to 5.5 V operation, with AC timing parameters (including tCLQV, tCHQX, tDISO) guaranteed across this entire voltage range up to 20 MHz. No derating is required; the device maintains full timing compliance and write endurance at minimum VCC, as validated in ST's DS4712 Rev 22 characterization data.
What happens if the Write Protect (W) pin is left floating?
The Write Protect (W) pin must be actively driven high or low - floating is undefined and may cause erratic behavior. If left unconnected, internal leakage or noise could toggle the hardware protection state, potentially freezing BP1/BP0 bits unexpectedly or disabling write protection entirely. ST recommends tying W to VCC (for default unprotected mode) or VSS (for default protected mode) via a pull-up/down resistor, per Section 3.6 of DS4712.
M95256-RDW6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95256-RDW6TP FAQ
1.How can I place an order for M95256-RDW6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95256-RDW6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95256-RDW6TP reliable?
The price and inventory of M95256-RDW6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95256-RDW6TP is usually 5 days.
3.What payment methods are accepted for M95256-RDW6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95256-RDW6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95256-RDW6TP?
M95256-RDW6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95256-RDW6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95256-RDW6TP?
For technical support, including M95256-RDW6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95256-RDW6TP requirements.
6.How does Aetrix verify that M95256-RDW6TP is sourced from the original manufacturer or authorized distributors?
All M95256-RDW6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95256-RDW6TP meets industry standards.
7.What is the process for return or replacement of M95256-RDW6TP?
All M95256-RDW6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95256-RDW6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95256-RDW6TP part is unused and in its original packaging.
Return procedure for M95256-RDW6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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