STMicroelectronics M95320-DRMF3TG/K

Overview

M95320-DRMF3TG/K from STMicroelectronics is an AEC-Q100 Grade 0 automotive serial SPI EEPROM with 32-Kbit (4-Kbyte) capacity, 32-byte page size, and extended temperature operation up to +145°C. It features Schmitt-trigger inputs, software/hardware write protection, embedded ECC, and a lockable 32-byte identification page - deployed in engine control units, battery management systems, and ADAS sensor modules.

For engineers reviewing the M95320-DRMF3TG/K datasheet, M95320-DRMF3TG/K pinout, M95320-DRMF3TG/K application, or M95320-DRMF3TG/K equivalent, key selection criteria include high-temp endurance (≥0.4M write cycles at 145°C), 20 MHz SPI clock support, ECOPACK2-compliant WFDFPN8 package, and status register-controlled block protection.

Technical Context

This device implements a true EEPROM array organized as 128 pages × 32 bytes (4096 × 8 bits), with dedicated ECC logic for enhanced data integrity during read/write operations. The identification page (32 bytes) supports permanent locking via LID instruction and stores ST-manufactured ID codes (0x20, 0x00, 0x0C) plus user-defined parameters.

It operates in standard SPI modes CPOL=0/CPHA=0 and CPOL=1/CPHA=1, with input latching on rising C edge and output shifting on falling C edge. Hold mode pauses communication without resetting the clock sequence, requiring HOLD low and C low to activate, and supports seamless resumption after release.

Key Specifications

Pinout & Package

Package: WFDFPN8 (2 mm × 3 mm, 0.5 mm pitch, ECOPACK2-compliant).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar automotive EEPROM applications.

Compared with AT25DF321A-MAHN-T and BR24G32FJ-3GE2, M95320-DRMF3TG/K uniquely delivers Grade 0 qualification, embedded ECC, lockable ID page, and HOLD functionality - making it the only option for ASIL-B-compliant, high-temp, SPI-based parameter storage in powertrain and ADAS.

Availability

M95320-DRMF3TG/K is available at Aetrix Electronics and suitable for engine control units, battery management systems, advanced driver assistance systems, and automotive lighting control modules requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for M95320-DRMF3TG/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for automotive, industrial, and consumer markets.

The M95320 series belongs to ST's automotive-grade serial EEPROM product line, engineered specifically for mission-critical data storage in extreme thermal environments - emphasizing reliability, ECC integrity, and AEC-Q100 compliance from design through qualification.

FAQ

What is the function of the HOLD pin, and how does it differ from chip select (S)?

The HOLD pin pauses active SPI communication without deselecting the device or resetting the internal address counter - allowing external controllers to temporarily suspend transfers while retaining context. Unlike chip select (S), which fully deselects the device and forces Q into high-Z, HOLD maintains S low and preserves clock synchronization, enabling seamless resumption after release. Activation requires HOLD low and C low simultaneously.

How does the identification page differ from the main memory array?

The identification page is a dedicated 32-byte region separate from the main 4-Kbyte array, pre-programmed by ST with device ID codes (0x20, 0x00, 0x0C) and reserved for application-specific parameters. It supports WRID and RDID instructions and can be permanently locked in read-only mode using the LID instruction - preventing accidental or malicious overwrite of calibration or security-critical data.

What protection mechanisms prevent unintended writes to the memory array?

Three layered protections exist: (1) Software write enable (WREN instruction required before any WRITE/WRSR/WRID), (2) Status register block protection (BP1/BP0 bits restrict write access to upper quarter/half/full array), and (3) Hardware write protect (W pin disables status register writes when SRWD = 1 and W = low). These operate independently and concurrently to enforce robust data integrity.

Is the M95320-DRMF3TG/K compatible with standard SPI peripherals on common MCUs?

Yes - it supports both SPI Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1), matching most ARM Cortex-M, Renesas RH850, and Infineon AURIX MCU SPI peripherals. Input data is latched on the rising clock edge, and output data appears on the falling edge - aligning with standard SPI timing requirements without requiring custom firmware bit-banging.