My Inquiry
My Account
Vishay Siliconix SI9122EDQ-T1-E3
.jpg)
- Part No.:
- SI9122EDQ-T1-E3
- Manufacturer:
- Vishay Siliconix
- Category:
- DC DC Switching Controllers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SI9122EDQ-T1-E3.pdf
- Description:
- IC REG CTRLR HALF-BRIDGE 20TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,546
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI9122EDQ-T1-E3 from Vishay Siliconix is a 500-kHz half-bridge DC/DC controller IC with integrated secondary synchronous rectification drivers, designed for fixed telecom power systems (36–75 V input) delivering <3.3 V outputs. It integrates ±1 A primary high-/low-side gate drivers, programmable dead-time control via BBM pin, voltage-mode PWM with feedforward, and current sensing on the primary low-side MOSFET source. It enables >90% efficiency in intermediate bus converters and brick modules.
For engineers reviewing the SI9122EDQ-T1-E3 datasheet, SI9122EDQ-T1-E3 pinout, SI9122EDQ-T1-E3 application, or SI9122EDQ-T1-E3 equivalent, key selection considerations include its TSSOP-20 package, 36–75 V input range, 3.3 V reference output, 500 kHz nominal oscillator frequency set by ROSC, and dual-stage synchronous rectifier timing coordination with programmable break-before-make delay.
Technical Context
The SI9122EDQ-T1-E3 implements voltage-mode control with feedforward compensation, using VINDET to scale duty cycle against input voltage variations. Its error amplifier accepts inverted feedback (0–2 V at EP) from an optocoupler on the secondary side, enabling isolated regulation of low-voltage outputs.
It features dual-loop protection: primary current limiting via CS1/CS2 differential sensing (100 mV lower/150 mV upper threshold), and thermal shutdown at 135 °C. The BBM circuit uses an external resistor (22–50 kΩ) to set non-overlapping delays between primary (DH/DL) and secondary (SRH/SRL) drive signals, preventing transformer shorting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 36 V to 75 V - supports fixed telecom bus; withstands 80 V continuous, 100 V transient |
| Oscillator Frequency | 200 kHz to 500 kHz - set by external ROSC resistor (30–72 kΩ); 500 kHz nominal minimizes magnetics size |
| Reference Output | 3.3 V ±30 mV - stable internal bandgap reference for feedback loop; 0.1 µF decoupling required |
| Primary Driver Output | ±1 A peak - drives high-/low-side N-MOSFETs directly; DH uses bootstrap (BST/LX), DL referenced to PGND |
| Secondary Drive Capability | ±100 mA peak - provides sequenced SRH/SRL signals for pulse-transformer-coupled synchronous rectifiers |
| Current Sense Thresholds | 100 mV (lower), 150 mV (upper) - sets primary overcurrent limits; enables constant-current startup into capacitive loads |
| Break-Before-Make Delay | Programmable via BBM pin - 22–50 kΩ resistor sets tBBM1/tBBM2 (48 ns typical at 33 kΩ, 25 °C) |
| Operating Temperature | −40 °C to +85 °C - rated for industrial ambient; OTP deactivates at 113 °C after 135 °C trip |
Pinout & Package
TSSOP-20 package (JEDEC MO-153, 6.5 mm × 4.4 mm, 0.65 mm pitch), lead (Pb)-free, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | High-voltage start-up supply input | Connects to telecom bus; powers internal pre-regulator during startup before VCC is established |
| REG_COMP | External PNP pass transistor compensation | Stabilizes high-voltage pre-regulator loop when using external PNP; requires small capacitor (≤1 nF) |
| VCC | Internal logic and driver supply | 10.5–13.2 V operating range; clamped at 14.5 V; requires ≥4.7 µF bulk capacitance |
| VREF | 3.3 V precision reference output | Supplies optocoupler LED or secondary-side error amp; disabled in shutdown mode |
| GND | Analog ground reference | Signal return for VREF, EP, ROSC, CL_CONT; separate from PGND to minimize noise coupling |
| ROSC | Oscillator frequency programming node | Resistor to GND sets fOSC (200–500 kHz); 30 kΩ = 500 kHz nominal |
| EP | Inverted error amplifier input | 0–2 V input controls duty cycle inversely; 0 V = max duty, 2 V = min duty; requires optocoupler interface |
| VINDET | Input voltage monitor and feedforward input | Resistive divider from VIN sets UVLO (7.15–9.8 V) and provides line-voltage feedforward |
| CS1 / CS2 | Differential current sense inputs | Monitor voltage across low-side primary sense resistor; CS2 positive, CS1 negative |
| CL_CONT | Current limit compensation node | Capacitor here sets foldback response time; discharged during overload to reduce duty/frequency |
| BBM | Break-Before-Make timing resistor connection | 22–50 kΩ to GND programs non-overlap delay between primary and secondary drive edges |
| SS | Soft-start capacitor connection | 20 µA internal current charges external CSS to 8 V; longer time reduces inrush stress |
| SRL / SRH | Secondary synchronous rectifier drive outputs | Drive center-tapped pulse transformer; SRL/SRH phase relationship controls rectifier sequencing |
| PGND | Power ground return | Return path for DH, DL, SRH, SRL drivers; must be low-inductance, separate from analog GND |
| DL | Low-side primary gate driver output | Drives N-MOSFET source to PGND; 1 A sink/source capability; initiates bootstrap charging |
| LX | Half-bridge switch node | Connects to high-side MOSFET source and transformer primary; critical for BST capacitor charging |
| DH | High-side primary gate driver output | Bootstrapped drive (VBST referenced to LX); requires external diode/capacitor network |
| BST | Bootstrap supply input | Accepts charged capacitor (VBST ≈ LX + VCC); supplies DH driver high-side rail |
| EP | Error amplifier input (repeated for clarity) | Same as above; dedicated pin for feedback signal injection into control loop |
Key Features
| Feature | Design Value |
|---|---|
| Integrated ±1 A primary drivers | Eliminates need for external gate driver ICs; supports direct drive of high-current N-MOSFETs in half-bridge |
| Programmable BBM timing | Prevents shoot-through between primary and secondary MOSFETs using user-defined resistor; avoids transformer shorting |
| Voltage feedforward compensation | Uses VINDET signal to dynamically adjust duty cycle vs. input line variation, improving transient response and stability |
| Frequency foldback under overload | Reduces switching frequency to ~100 kHz during severe overcurrent, maintaining constant current without tail currents |
| Advanced startup current control | Enables controlled inrush into large output capacitors or parallel supplies; prevents VCC collapse during soft-start |
| 135 °C thermal shutdown | OTP protection with 22 °C hysteresis (113 °C restart) ensures safe operation in high-ambient telecom environments |
Applications
| Intermediate Bus Converter | Brick Converter Module |
|---|---|
Use Scenario: Step-down conversion from 48 V telecom bus to 3.3 V or 5 V intermediate rails feeding point-of-load regulators. IC Role / Device Role / Timing Role: Half-bridge controller coordinating primary switching and secondary synchronous rectification with precise BBM timing. Use Value: Achieves >92% efficiency at full load due to low-RDS(on) MOSFET drive and minimized dead-time losses. |
Use Scenario: Compact, isolated 50–100 W DC/DC module used in networking equipment and base stations. IC Role / Device Role / Timing Role: Core timing and drive controller managing high-frequency (500 kHz) half-bridge operation and transformer-isolated SR timing. Use Value: Enables high power density via 500 kHz operation and eliminates Schottky losses on secondary side. |
| Network Card Power Supply | Distributed Power System |
Use Scenario: On-board 12 V or 5 V generation for FPGA, ASIC, or PHY ICs on telecom line cards with strict thermal limits. IC Role / Device Role / Timing Role: Primary-side controller providing regulated output while interfacing with secondary-side optocoupler feedback. Use Value: Stable 3.3 V reference and robust current limiting ensure reliable startup into large capacitive loads. |
Use Scenario: Centralized 48 V input powering multiple isolated 3.3 V/5 V/12 V outputs across a chassis via intermediate bus architecture. IC Role / Device Role / Timing Role: Controller for each isolated converter stage, synchronizing secondary rectification to maximize system-level efficiency. Use Value: Programmable ROSC and BBM allow optimization across varying load and thermal conditions in multi-rail systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar half-bridge DC/DC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28950PW | 4-phase interleaved controller with adaptive dead-time; no integrated secondary drivers; requires external SR controllers | Targets higher-power (>200 W), multi-phase telecom PSUs; lacks native synchronous rectifier timing coordination | Choose UCC28950PW when scaling beyond 100 W or requiring phase interleaving; SI9122EDQ-T1-E3 better suits compact single-stage designs with integrated SR drive. |
| LT3748IMS | Isolated flyback controller with integrated MOSFET gate drivers; no half-bridge topology support; operates up to 1 MHz | Designed for flyback/isolated forward topologies; not compatible with half-bridge transformer configurations | Choose LT3748IMS for lower-power isolated supplies (<60 W) where flyback simplicity outweighs half-bridge efficiency; SI9122EDQ-T1-E3 remains optimal for fixed-input telecom half-bridge systems. |
Compared with UCC28950PW and LT3748IMS, the SI9122EDQ-T1-E3 uniquely integrates both primary half-bridge drivers and secondary synchronous rectifier timing in a single TSSOP-20 package, eliminating external SR driver complexity and enabling >90% efficiency at sub-3.3 V outputs without topology redesign.
Availability
SI9122EDQ-T1-E3 is available at Aetrix Electronics and suitable for intermediate bus converters, brick modules, and distributed power systems requiring stable component supply in telecom infrastructure and industrial embedded applications.
Supply support for SI9122EDQ-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete power MOSFETs, diodes, optoelectronics, and analog ICs for high-reliability power conversion and signal conditioning.
The Si9122E product line was engineered specifically for fixed telecom DC/DC conversion, emphasizing high efficiency at low output voltages (<3.3 V), robust thermal management, and simplified synchronous rectifier implementation in half-bridge topologies.
FAQ
What is the recommended external ROSC resistor value to achieve 500 kHz operation for SI9122EDQ-T1-E3?
The SI9122EDQ-T1-E3 achieves 500 kHz nominal oscillator frequency with a 30 kΩ resistor connected from ROSC pin to GND. This value is specified in the Recommended Operating Range table and confirmed in Typical Characteristics (Figure on p.12). Deviations outside 30–72 kΩ shift frequency beyond 200–500 kHz range. Always verify actual frequency with oscilloscope measurement during prototype validation, as layout parasitics and temperature affect final accuracy.
How does the SI9122EDQ-T1-E3 implement synchronous rectification timing coordination?
The SI9122EDQ-T1-E3 generates non-overlapping SRH and SRL signals using an internal programmable break-before-make (BBM) timer. An external resistor on the BBM pin sets delay times (e.g., 48 ns tBBM1 at 33 kΩ, 25 °C) to prevent simultaneous conduction of primary and secondary MOSFETs. This avoids transformer shorting and ensures safe commutation. Timing relationships are detailed in Figure 3 and Technical Description section on page 2 of the datasheet.
Can SI9122EDQ-T1-E3 operate with input voltages below 36 V?
No. The SI9122EDQ-T1-E3 is specified for 36–75 V input only. Below 36 V, the internal pre-regulator cannot establish sufficient VCC bias, and UVLO (7.15–9.8 V) prevents startup. Attempting operation at 24 V or 12 V will result in no switching. For lower-input applications, consider alternative controllers such as the UCC28950 or LTC3722, which support wider VIN ranges.
What is the function of the EP pin on SI9122EDQ-T1-E3, and how should it be interfaced?
The EP pin is the inverted error amplifier input. It accepts 0–2 V from an optocoupler's phototransistor collector, where 0 V commands maximum duty cycle and 2 V commands minimum. It must be driven through an optocoupler for isolation; direct connection violates safety requirements. The internal inverting amplifier converts this signal to control the PWM generator. No external pull-up or bias is needed-interface per Figure 1 and Functional Block Diagram on page 1.
Does SI9122EDQ-T1-E3 support current-mode control, or is it strictly voltage-mode?
The SI9122EDQ-T1-E3 operates primarily in voltage mode but incorporates current-limiting functionality that overrides voltage-mode control during overloads. Under normal conditions, it uses voltage-mode PWM with feedforward. During overcurrent, the CL_CONT node takes control, reducing duty cycle first, then folding back frequency to ~100 kHz. This hybrid behavior provides fast fault response without requiring full current-mode loop design.
SI9122EDQ-T1-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Type:
- Transistor Driver
- Function:
- Step-Up/Step-Down
- Output Configuration:
- Positive, Isolation Capable
- Topology:
- Half-Bridge
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 10.5V ~ 13.2V
- Frequency - Switching:
- 500kHz
- Duty Cycle (Max):
- 91%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Sequencing, Soft Start
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP
SI9122EDQ-T1-E3 FAQ
1.How can I place an order for SI9122EDQ-T1-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI9122EDQ-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI9122EDQ-T1-E3 reliable?
The price and inventory of SI9122EDQ-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI9122EDQ-T1-E3 is usually 5 days.
3.What payment methods are accepted for SI9122EDQ-T1-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI9122EDQ-T1-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI9122EDQ-T1-E3?
SI9122EDQ-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI9122EDQ-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI9122EDQ-T1-E3?
For technical support, including SI9122EDQ-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI9122EDQ-T1-E3 requirements.
6.How does Aetrix verify that SI9122EDQ-T1-E3 is sourced from the original manufacturer or authorized distributors?
All SI9122EDQ-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI9122EDQ-T1-E3 meets industry standards.
7.What is the process for return or replacement of SI9122EDQ-T1-E3?
All SI9122EDQ-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SI9122EDQ-T1-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI9122EDQ-T1-E3 part is unused and in its original packaging.
Return procedure for SI9122EDQ-T1-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI9122EDQ-T1-E3 Tags
-
UCC28C45DR
Texas Instruments
-
UCC28C40DR
Texas Instruments
-
UCC28C43DR
Texas Instruments
-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments
-
MIC2102YML-TR
Microchip Technology
-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments
-
LM5155DSSR
Texas Instruments
-
LM25085MYX/NOPB
Texas Instruments
-
UCC2813DTR-0
Texas Instruments
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
